AT93C46C-10PI-2.7

7
AT93C46C
1122DSEEPR08/02
Timing Diagrams
Synchronous Data Timing
Note: This is the minimum SK period.
8
AT93C46C
1122DSEEPR08/02
READ Timing
EWEN Timing
(1)
Note: 1. Requires a minimum of nine clock cycles.
EWDS Timing
(1)
Note: 1. Requires a minimum of nine clock cycles.
Organization Key for Timing Diagrams
I/O
AT93C46C
x16
A
N
A
5
D
N
D
15
High Impedance
t
CS
CS
11
...
001
SK
DI
t
CS
CS
t
CS
SK
DI 1 0
000
...
9
AT93C46C
1122DSEEPR08/02
WRITE Timing
WRAL Timing
(1)(2)
Notes: 1. Valid only at V
CC
= 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
SK
CS
t
CS
t
WP
11
A
N
D
N
0A0D0
... ...
DI
DO
HIGH IMPEDANCE
BUSY
READY
CS
SK
DI
DO
HIGH IMPEDANCE
BUSY
READY
1 0 0 1 ... D
N
t
CS
t
WP
... D00

AT93C46C-10PI-2.7

Mfr. #:
Manufacturer:
Description:
IC EEPROM 1K SPI 2MHZ 8DIP
Lifecycle:
New from this manufacturer.
Delivery:
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