CAT5171TBI-50GT3

CAT5171
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10
START CONDITION
SDA
STOP CONDITION
SCL
Figure 16. Start/Stop Condition
ACKNOWLEDGE
1
START
SCL FROM
MASTER
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 17. Acknowledge Condition
CAT5171
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11
INSTRUCTION AND REGISTER DESCRIPTION
Slave Address Byte
The first byte sent to the CAT5171 from the
master/processor is called the Slave Address Byte. The most
significant six bits of the slave address are a device type
identifier. For the CAT5171, these bits are fixed at 010110.
The next bit, AD0, is the first bit of the internal slave
address and must match the physical device address which
is defined by the state of the AD0 input pin for the CAT5171
to successfully continue the command sequence. Only the
device which slave address matches the incoming device
address sent by the master executes the instruction. The AD0
input can be actively driven by CMOS input signals or tied
to the supply voltage or ground.
The next bit, R/W
, indicates whether this command
corresponds to a Write or Read instruction. To write into the
Wiper control register, R/W
bit is set to a logic low; while a
read from the wiper register is done with the bit high.
Wiper Control
The CAT5171 contains one 8-bit Wiper Control Register
(WCR). The Wiper Control Register output is decoded to
select one of 256 switches along its resistor array. The
contents of the WCR may be written by the host via Write
instruction.
The Wiper Control Register is a volatile register that loses
its contents when the CAT5171 is powered-down. Upon
power-up, the wiper is set to midscale and may be
repositioned anytime after the power has become stable.
Instructions
Write and Read instructions are respectively three and two
bytes in length. The basic sequence of the two instructions
is illustrated in Table 11 and 12.
In write mode, the second byte is the instruction byte. The
first bit (MSB) of the instruction byte is a don’t care. The
second MSB, RS, is the midscale reset. A logic high on this
bit moves the wiper to the center tap. The third MSB, SD, is
a shutdown bit. A logic high causes an open circuit at
terminal A, and short the wiper terminal W to terminal B.
The “shutdown” operation does not change the contents of
the wiper register. When the shutdown bit, SD, goes back to
a logic low, the previous wiper position is restored. Also
during shutdown, new settings can be programmed. As soon
as the device is returned from shutdown, the wiper position
is set according to the wiper register value.
Two CAT5171 on a Single Bus
When needed, it is possible to connect two CAT5171
potentiometers on the same I
2
C bus and be able to address
each one independently. Each device can be set to a unique
address by using the AD0 input pin. One device AD0 pin is
connected to ground, and the other device AD0 pin is tied to
the supply voltage.
Table 11. Write
S 0 1 0 1 1 0 AD0 W A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
S
T
A
R
T
0 1 0 1 1 0 AD0
A
C
K
XXXXX
A
C
K
SDA
S
T
O
P
A
C
K
D7
Slave Address Byte
Instruction Byte Data Byte
RS SD X D6 D5 D4 D3 D2 D1 D0
R/W
Table 12. READ
S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
S
T
A
R
T
0 1 0 1 1 0 AD0
A
C
K
SDA
S
T
O
P
N
C
K
D7
Slave Address Byte
Data Byte
D6 D5 D4 D3 D2 D1 D0
R/W
A
Legend
S = Start
P = Stop
A = Acknowledge
AD0 = Address bit 0, needed when using two
potentiometers on the same I
2
C bus.
D = Data bit
R = Read (bit is 1 for Read instruction)
W
= Write (bit is 0 for Write instruction)
RS = When the bit is 1, the wiper position is moved
to mid-scale 0x80
SD = Shut Down:
0: normal operation
1: wiper is parked at B terminal and terminal A
is open circuit.
X = Don’t Care
CAT5171
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12
PACKAGE DIMENSIONS
SOT−23, 8 Lead
CASE 527AK
ISSUE A
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
SYMBOL
EE1
A2
A3
A1
eb
D
c
A
TOP VIEW
SIDE VIEW END VIEW
L1 L2L
PIN #1 IDENTIFICATION
MIN NOM MAX
q
A
A1
A2
b
c
D
E
E1
L
L2
0.00
0.90
0.28
0.08
2.90 BSC
1.60 BSC
0.45
1.45
0.15
1.30
0.38
0.22
0.25 REF
1.10
2.80 BSC
L1 0.60 REF
e
0.30 0.60
0.65 BSC
0.90
θ0° 8°
A3 0.60 0.80
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CAT5171TBI-50GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs Linear Single 256 Taps Non Buffer
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