CAT5171TBI-50GT3

CAT5171
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7
BASIC OPERATION
The CAT5171 is a 256-position digitally controlled
potentiometer. When power is first applied, the wiper
assumes a mid-scale position. Once the power supply is
stable, the wiper may be repositioned via the I
2
C compatible
interface.
PROGRAMMING: VARIABLE RESISTOR
Rheostat Mode
The resistance between terminals A and B, R
AB
, has a
nominal value of 50 kW or 100 kW and has 256 contact
points accessed by the wiper terminal, plus the B terminal
contact. Data in the 8-bit Wiper register is decoded to select
one of these 256 possible settings.
The wipers first connection is at the B terminal,
corresponding to control position 0x00. Ideally this would
present a 0 W between the Wiper and B, but just as with a
mechanical rheostat there is a small amount of contact
resistance to be considered, there is a wiper resistance
comprised of the R
ON
of the FET switch connecting the
wiper output with its respective contact point. In CAT5171
this ‘contact’ resistance is typically 50 W. Thus a connection
setting of 0x00 yields a minimum resistance of 50 W
between terminals W and B.
For a 100 kW device, the second connection, or the first tap
point, corresponds to 441 W (R
WB
= R
AB
/256 + R
W
= 390.6
+ 50 W) for data 0x01. The third connection is the next tap
point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on.
Figure 11 shows a simplified equivalent circuit where the
last resistor string will not be accessed; therefore, there is
1 LSB less of the nominal resistance at full scale in addition
to the wiper resistance.
Figure 11. CAT5171 Equivalent Digital POT Circuit
R
S
Wiper
Register
and
Decoder
A
W
B
R
S
R
S
R
S
The equation for determining the digitally programmed
output resistance between W and B is
R
WB
+
D
256
R
AB
) R
W
(eq. 1)
where D is the decimal equivalent of the binary code loaded
in the 8-bit Wiper register, R
AB
is the end-to-end resistance,
and R
W
is the wiper resistance contributed by the on
resistance of the internal switch.
In summary, if R
AB
= 100 kW and the A terminal is open
circuited, the following output resistance R
WB
will be set for
the indicated Wiper register codes:
Table 9. CODES AND CORRESPONDING R
WB
RESISTANCE FOR R
AB
= 100 kW, V
DD
= 5 V
D (Dec.)
R
WB
(W)
Output State
255 99,559 Full Scale (R
AB
– 1 LSB + R
W
)
128 50,050 Midscale
1 441 1 LSB
0 50 Zero Scale
(Wiper Contact Resistance)
Be aware that in the zero-scale position, the wiper
resistance of 50 W is still present. Current flow between W
and B in this condition should be limited to a maximum
pulsed current of no more than 20 mA. Failure to heed this
restriction can cause degradation or possible destruction of
the internal switch contact.
Similar to the mechanical potentiometer, the resistance of
the digital POT between the wiper W and terminal A also
produces a digitally controlled complementary resistance
R
WA
. When these terminals are used, the B terminal can be
opened. Setting the resistance value for R
WA
starts at a
maximum value of resistance and decreases as the data
loaded in the latch increases in value. The general equation
for this operation is
R
WA
(D) +
256 * D
256
R
AB
) R
W
(eq. 2)
For R
AB
= 100 kW and the B terminal open circuited, the
following output resistance R
WA
will be set for the indicated
Wiper register codes.
Table 10. CODES AND CORRESPONDING R
WA
RESISTANCE FOR R
AB
= 100 kW, V
DD
= 5 V
D (Dec.)
R
WA
(W)
Output State
255 441 Full Scale
128 50,050 Midscale
1 99,659 1 LSB
0 100,050 Zero Scale
Typical device to device resistance matching is lot
dependent and may vary by up to ±20%.
CAT5171
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8
ESD Protection
GND
LOGIC
Digital
Input
GND
Potentiometer
Figure 12. ESD Protection Networks
W, A, B
Terminal Voltage Operating Range
The CAT5171 V
DD
and GND power supply define the
limits for proper 3-terminal digital potentiometer operation.
Signals or potentials applied to terminals A, B or the wiper
must remain inside the span of V
DD
and GND. Signals
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
W, A, B
CAT5171
LOGIC
GND
Figure 13.
V
DD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 12), it is
recommended that V
DD
/GND be powered before applying
any voltage to terminals A, B, and W. The ideal power−up
sequence is: GND, V
DD
, digital inputs, and then V
A/B/W
. The
order of powering V
A
, V
B
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01 mF to
0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
CAT5171
GND
+
10 mF
0.1 mF
Figure 14. Power Supply Bypassing
V
DD
V
DD
C
3
C
1
CAT5171
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9
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5171 will be considered a slave device
in all applications.
START Condition
The START condition precedes all commands to the
device, and is defined as a high to low transition of SDA
when SCL is high. The CAT5171 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
A low to high transition of SDA when SCL is high
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular slave device it is requesting. The six most
significant bits of the 8-bit slave address are fixed as 010110
for the CAT5171. The next bit (AD0) is the device least
significant address bit and defines which device the Master
is accessing. Up to two devices may be individually
addressed by the system. Typically, +5 V (V
DD
) or ground
is hard-wired to the AD0 pin to establish the device’s
address.
After the Master sends a START condition and the slave
address byte, the CAT5171 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT5171 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5171 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5171 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Write Operation
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte. After receiving another
acknowledge from the Slave, the Master device transmits
the data to be written into the wiper register. The CAT5171
acknowledges once more and the Master generates the
STOP condition.
Figure 15. Bus Timing Diagram
t
HIGH
SCL
SDA IN
SDA OUT
t
LOW
t
F
t
LOW
t
R
t
BUF
t
SU:STO
t
SU:DAT
t
HD:DAT
t
HD:STA
t
SU:STA
t
AA
t
DH

CAT5171TBI-50GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs Linear Single 256 Taps Non Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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