10
FN6111.3
February 5, 2008
FIGURE 15. TURN - ON TIME vs SUPPLY VOLTAGE FIGURE 16. TURN - OFF TIME vs SUPPLY VOLTAGE
FIGURE 17. FREQUENCY RESPONSE FIGURE 18. CROSSTALK AND OFF ISOLATION
FIGURE 19. ON LEAKAGE vs SWITCH VOLTAGE
FIGURE 20. OFF LEAKAGE vs SWITCH VOLTAGE
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
t
ON
(ns)
V+ (V)
1 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
50
100
150
200
+85
°C
-40°C
+25°C
t
OFF
(ns)
V+ (V)
1
1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
50
100
150
200
+85°C
-40°C
+25°C
FREQUENCY (Hz)
0
-20
NORMALIZED GAIN (dB)
GAIN
PHASE
V+ = 3V
0
20
40
60
80
100
PHASE (°)
1M 10M 100M 600M
V
IN
= 0.2V
P-P
to 2V
P-P
R
L
= 50Ω
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V+ = 3V
I
ON
(nA)
V
COM/NX
(V)
012345
-100
-50
0
50
100
+25°C
+85°C
V+ = 4.5V
I
OFF
(nA)
V
NX
(V)
012345
-150
-100
-50
0
50
+85°C
+25°C
V+ = 4.5V
V
COM
= 0.3V
ISL8499
11
FN6111.3
February 5, 2008
FIGURE 21. SUPPLY CURRENT vs VLOGIC
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: To Ground or Float)
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
I
ON
(μA)
V
IN1-4
(V)
12345
0
50
100
150
200
V+ = 4.2V
Sweeping Both Logic Inputs
ISL8499
12
FN6111.3
February 5, 2008
ISL8499
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm
(0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA
E1
D
N
123
-B-
0.10(0.004) C AM BS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
a
0
o
8
o
0
o
8
o
-
Rev. 1 2/02

ISL8499IRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs LW THRESHOLD VERQD DPDT SWITCH 16LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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