ISL6422BERZ-T Datasheet ISL6422BERZ-T, ISL6422BERZ, ISL6422BEVEZ | P10-P12

FN6486.2

September 8, 2015

Functional Description

The ISL6422B dual output voltage regulator makes an ideal

choice for advanced satellite set-top box and personal video

recorder applications. Both supply and control voltage

outputs for two low-noise blocks (LNBs) are available

simultaneously in any output configuration. The device

utilizes built-in DC/DC step up converters that, from a single

supply source ranging from 8V to 14V, generate the voltages

that enable the linear post-regulators to work with a

minimum of dissipated power. An undervoltage lockout

circuit disables the device when V

drops below a fixed

threshold (7.5V typical).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of

22kHz in accordance with DiSEqC (EUTELSAT) standards.

No further adjustment is required. The tone oscillator can be

controlled either by the I

C interface (ENT1, ENT2 bit) or by a

dedicated pin (EXTM1, EXTM2) that allows immediate

DiSEqC data encoding separately for each LNB. All the

functions of this IC are controlled via the I

C bus by writing to

the system registers. The same registers can be read back,

and four bits will report the diagnostic status. The internal

oscillator operates the converters at twenty times the 22k tone

frequency. The device offers full I

C compatibility and

supports 2.5V, 3.3V or 5V logic, and up to 400kHz operation.

If the Tone Enable (ENT1, ENT2) bit is set LOW and the

MSEL1, MSEL2 bits set LOW through I

C, then the EXTM1,

EXTM2 terminal activates the internal tone signal,

modulating the DC output with a 680mV

P-P

typ symmetrical

tone waveform. The presence of this signal usually provides

the LNB with information about the band to be received.

Burst coding of the tone can be accomplished due to the fast

response of the EXTM1, EXTM2 input and rapid tone

response. This allows implementation of the DiSEqC

(EUTELSAT) protocols.

When the ENT1/2 bit is set HIGH, a continuous 22kHz tone

is generated regardless of the EXTM1, EXTM2 pin logic

status for the corresponding regulator channel (LNB-A or

LNB-B). The ENT1, ENT2 bit must be set LOW when the

EXTM1 and/or EXTM2 pin is used for DiSEqC encoding.

The EXTM1 and EXTM2 pins also accept an externally

modulated tone command when the MSEL1 and MSEL2 I

bit is set high.

DiSEqC Decoder

TDIN1, TDIN2 are the inputs to the tone decoders of

Channels 1 and 2 respectively. They accept the tone signal

derived from V

OUT

thru the 10nF decoupling capacitor. The

detector threshold can be set to 200mV max in the Receive

mode and to 400mV min in the Transmit mode by means of

the logic presented to the TXT1, TXT2 pin. If tone is

detected, the open drain pins TDOUT1, TDOUT2 are

asserted low. This also enables the tone diagnostics to be

performed, apart from the normal tone detection function.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.75µF. In order to minimize the power

dissipation, the output voltage of the internal step-up

converter is adjusted to allow the linear regulator to work at

minimum dropout.

When the device is put in the shutdown mode (EN1,

EN2 = LOW), both PWM power blocks are disabled. (i.e.

when EN1 = 0, PWM1 is disabled, and when EN2 = 0,

PWM2 is disabled).

When the regulator blocks are active (EN1, EN2 = HIGH and

VSPEN1, VSPEN2 = LOW), the output can be controlled via

C logic to be 13V/14V or 18V/19V (typical) by means of the

VTOP1, VTOP2 and VBOT1, VBOT2 bits (Voltage Select)

for remote controlling of non-DiSEqC LNBs.

When the regulator blocks are active (EN1, EN2 = HIGH and

VSPEN1, VSPEN2 = HIGH), the VBOT1,VBOT2 and

SELVTOP1, SELVTOP2 pin will control the output between

13V and 14V and the VTOP1, VTOP2 and SELVTOP1,

SELVTOP2 pin will control the output between 18V and 19V.

Output Timing

The output voltage rise and fall times can be set by an the

external capacitor on the TCAP pin. The output rise and fall

times is given by Equation 1:

Where C is the TCAP value in nF, t is the required slew rate

in ms and V is the differential transition voltage from low

output voltage range to the high output range in Volts.

The recommended value for TCAP is 0.15µF. Too large a

value of TCAP prevents the output from rising to the nominal

value, within the soft-start time when the error amplifier is

released. Too small a value of the TCAP can cause high

peak currents in the boost circuit, for example, a 10V/ms

slew on a 80µF VSW capacitor with an inductor of 15µH can

cause a peak inductor current of approximately 2.3A.

Current Limiting

Dynamic current limiting block has five thresholds that can

be selected by the ISEL1H, ISEL2H , ISEL1L, ISEL2L ,

ISLE1R, ISLE2R bits of the SR. Refer to Table 8 and Table 9

for threshold selection using these bits. The DCL bit has to

be set to low for this mode of operation. In the dynamic

overcurrent mode a fault exceeding the selected overcurrent

threshold for a period greater than 51ms will shutdown the

output for 900ms, during which the I

C bit OLF is set HIGH.

At the end of 900ms, the OLF bit is returned to low state, a

soft-start cycle (~20ms long) is initiated to ramp VSW and

OUT

back up. If the fault is still present, the overcurrent will

327.6t

V

-----------------

(EQ. 1)

ISL6422B

FN6486.2

September 8, 2015

be reached early in the soft-start cycle and a 51ms shutdown

timer will be started again. If the fault is still present at the

end of the 51ms, the OLF bit is again set high and the device

once again enters the 900ms OFF time. This dynamic

operation can greatly reduce the power dissipation in a short

circuit condition, still ensuring excellent power-on start-up in

most conditions.

However, there could be some cases in which a highly

capacitive load on the output may cause a difficult start-up

when the dynamic protection is chosen. This can be solved

by initiating any power start-up in static mode (DCL = HIGH)

and then switching to the dynamic mode (DCL = LOW) after

a chosen amount of time. When in static mode, the OLF1,

OLF2 bit goes HIGH when the current clamp limit is reached

and returns LOW at the end of the initial power on soft-start.

In the static mode the output current through the linears is

limitted to 990mA typ.

When a 19.3V line is connected onto a VOUT1 or VOUT2 that

has been set to 13.3V, the linear will then enter a back current

limited state. When a back current of greater that 140mA typ

is sensed at the lower FET of the linear for a period greater

that 2ms, the output is disabled for a period of 50ms and the

BCF1, BCF2 bit are set. If the 19.3V remains connected, the

output will cycle through the ON = 2ms/OFF = 50ms. The

output will return to the setpoint when the fault is removed.

BCF bit is set high during the 50ms OFF period.

Thermal Protection

This IC is protected against overheating. When the junction

temperature exceeds +150°C (typical), the step-up converter

and the linear regulator are shut off and the OTF bit of the

SR is set HIGH. Normal operation is resumed and the OTF

bit is reset LOW when the junction is cooled down to +130°C

(typical).

If a part is repeatedly driven to the over-temperature

shutdown, the chip is latched off after the fourth occurance

and the I

C bit is latched HIGH and the FLT bar LOW. This

OTF counter and the FLT bar can be reset and the chip

restarted by either a power down/up and reload the I

C or

power can be left on and the reset accomplished by toggling

the I

C bit EN low then back HIGH.

External Output Voltage Selection

The output voltage can be selected by the I

C bus.

Additionally, the package offers two pins (SELVTOP1,

SELVTOP2) for independent 13V thru 19V output voltage

selection.

C Bus Interface for ISL6422B

(Refer to Philips I

C Specification, Rev. 2.1)

Data transmission from main microprocessor to the ISL6422B

(and vice versa) takes place through the two wire I

C bus

interface, consisting of the two lines, SDA and SCL. Both SDA

and SCL are bidirectional lines. They are connected to a

positive supply voltage via a pull-up resistor. (Pull-up resistors

to positive supply voltage must be externally connected). When

the bus is free, both lines are HIGH. The output stages of

ISL6422B will have an open drain/open collector in order to

perform the wired-AND function. Data on the I

C bus can be

transferred up to 100kbps in the standard-mode or up to

400kbps in the fast-mode. The level of logic “0” and logic “1”

depends value of V

as per the “Electrical Specifications”

table on page 5. One clock pulse is generated for each data bit

transferred.

Data Validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW. Refer to Figure 4.

START and STOP Conditions

As shown in Figure 5, START condition is a HIGH to LOW

transition of the SDA line while SCL is HIGH.

TABLE 1.

VSPEN1/2 VTOP1/2 VBOT1/2 SELVTOP1/2

VOUT1/2

(V)

0x0 013.3

0x1 014.3

00x 118.3

01x 119.3

100 x13.3

101 x14.3

110 x18.3

111 x19.3

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

FIGURE 4. DATA VALIDITY

ISL6422B

FN6486.2

September 8, 2015

The STOP condition is a LOW to HIGH transition on the SDA

line while SCL is HIGH. A STOP condition must be sent

before each START condition.

Byte Format

Every byte put on the SDA line must be eight bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most significant

bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on

the SDA line during the acknowledge clock pulse (Figure 6).

The peripheral that acknowledges has to pull-down (LOW)

the SDA line during the acknowledge clock pulse so that the

SDA line is stable LOW during this clock pulse (of course,

set-up and hold times must also be taken into account).

The peripheral which has been addressed has to generate

an acknowledge after the reception of each byte, otherwise

the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

The ISL6422B will not generate the acknowledge if the

POWER OK signal from the UVLO is LOW.

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the

microprocessor can use a simpler transmission; it waits one

clock without checking the slave acknowledging, and sends

the new data. Although, this approach is less protected from

error and decreases the noise immunity.

ISL6422B Software Description

Interface Protocol

The interface protocol is comprised of the following, as

shown below in Table 2:

• A start condition (S)

• A chip address byte (MSB on left; the LSB bit determines

read (1) or write (0) transmission) (the assigned I

C slave

address for the ISL6422B is 0001 00XX)

• A sequence of data (1 byte + Acknowledge)

• A stop condition (P)

System Register Format

• R, W = Read and Write bit

• R = Read-only bit

All bits reset to 0 at Power-On

NOTE: X = Bit not used

SDA

SCL

START

CONDITION

FIGURE 5. START AND STOP WAVEFORMS

STOP

CONDITION

SDA

SCL

FIGURE 6. ACKNOWLEDGE ON THE I

C BUS

ACKNOWLEDGE

FROM SLAVE

MSB

START

TABLE 2. INTERFACE PROTOCOL

S0001000R/WACK Data (8 bits) ACKP

TABLE 3. STATUS REGISTER 1 (SR1)

R, W R, W R, W R R R R R

SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1

TABLE 4. TONE REGISTER 2 (SR2)