NCP5269
http://onsemi.com
10
threshold voltage and restart the part. Please note this
protection function DOES NOT trigger the fault counter to
latch off the part.
Over Voltage Protection (OVP)
When VFB voltage is 200 mV (typical) above V
REF
voltage for over 1.5 ms blanking time, an OV fault is set. At
that moment, the top gate driver is turned off and the bottom
gate driver is turned on trying to discharge the output. The
bottom gate driver will be turned off when VFB drops below
under voltage threshold. EN resets or power recycle the
device can exit the fault. OVP is disabled during VID
changes.
Under Voltage Protection (UVP)
An UVP circuit monitors the VFB voltage to detect under
voltage event. The under voltage limit is 300 mV (typical)
below V
REF
voltage. If the VFB voltage is below this
threshold over 3.3 ms, an UV fault is set and the device is
latched off such that both top and bottom gate drives are off.
EN resets or power recycle the device can exit the fault. UVP
is delayed for soft start after EN goes high. UVP is disabled
during VID changes.
Power Good Monitor (PG)
NCP5269 provides window comparator to monitor the FB
voltage. The target voltage window and transition delay
times of the PGOOD comparator are ±5% (typ.) and 3.3−ms
delay for assertion (low to high), and ±10% (typ) and 1.5−ms
delay for de−assertion (high to low) during running. The PG
pin is open drain 5−mA pull down output. During startup,
PG stays low until the feedback voltage is within the
specified range for about 3.3 ms. To prevent a false alarm;
the power−good circuit is masked during any VID change.
The duration of the PG mask is set to approximately 425 ms
by an internal timer.
Over Current Protection (OCP)
The NCP5269 protects converter if over−current occurs.
The current through inductor is continuously monitored
with differential current sense. Current limit threshold
Vth_OC between CS+ and CS− is internally fixed to 30 mV.
The current limit can be programmed by inductor’s DCR
and current sensing resistor divider with Rs1 and Rs2.
The Rs1, Rs2 and C can be calculated as:
C @
ǒ
R
S1
ńńR
S2
Ǔ
+
L
DCR
The inductor peak current limit is:
I
LIM(Peak)
+
V
th_DC
k @ DCR
,wherek+
R
S2
R
S1
) R
S2
The DC current limit is:
I
LIM
+ I
LIM(Peak)
*
V
O
@
ǒ
V
in
* V
O
Ǔ
2 @ V
in
@ f
SW
@ L
where Vin is the input supply voltage of the power stage, and
fsw is normal switching frequency.
DCR
L
Rs1
Rs2
C
Vin
Vout
Vc
+
−
Figure 4. Inductor DCR Current Sensing Circuit
Figure 5 shows NTC resistor network to compensate the
temperature drift of DCR.
DCR
L
R
R1
RNTC
C
R2
Vin Vout
Vc
+
−
Figure 5. Inductor DCR Current Sensing Circuit with
Temperature Compensation Network
R
THE
If inductor current exceeds the current threshold, the
high−side gate driver will be turned off cycle−by−cycle. In
the mean time, an internal OC fault timer will be triggered.
If the fault still exists after about 8 clock cycles, the part
latches off, both the high−side MOSFET and the low−side
MOSFET are turned off. The fault remains set until the
system has shutdown and re−applied VCC and/or the enable
signal EN is toggled.
Pre−Bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP5269 supports pre−bias
start up by holding Low side FETs off till soft start ramp
reaches the FB pin voltage.
Thermal Shutdown
The NCP5269 protects itself from over heating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold, an
internal resistor will discharge Vref and the voltage at the
COMP pin will be pulled to GND, and both the upper and
lower MOSFETs will be shut OFF. When temperature drops
below threshold, the part will auto restart with soft− start
feature.
