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WM8761CBGED/R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
WM8761 Production Data
w
PD, Rev 4.6, October 2011
13
LEFT CHANNEL RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n321
n-2 n-1
LSB
MSB
n321
n-2 n-1
LSB
MSB
1 BCKIN
1 BCKIN
Figure 6 I
2
S Mode Timing Diagram
RIGHT JUSTIFIED MODE
The WM8761 supports word lengths of 24-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used
as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected
word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of
word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
LEFT CHANNEL RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
24
321
22 23
LSBMSB
24
321
22 23
LSBMSB
Figure 7 Right Justified Mode Timing Diagram
DSP MODE
A DSP compatible, time division multiplexed format is also supported by the WM8761. This format
is of the type where a ‘synch’ pulse is followed by two data words (left and right) of predetermined
word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCIN, and DSP mode is
auto-detected by the shorter than normal duration of the LRCIN. If LRCIN is of 4 BCKIN or less
duration, the DSP compatible format is selected. Early and Late clock formats are supported,
selected by the state of the FORMAT pin.
WM8761 Production Data
w
PD, Rev 4.6, October 2011
14
Figure 8 DSP ‘Late’ Mode Timing
Figure 9 DSP ‘Early’ Mode Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8761 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8761 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCIN, although the WM8761 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
(LRCIN)
MASTER CLOCK FREQUENCY (MHz) (MCLK)
128FS 256fs 512fs 768fs
32kHz 4.096 8.192 16.384 24.576
44.1kHz 5.6448 11.2896 22.5792 33.8688
48kHz 6.144 12.288 24.576 36.864
96kHz 12.288 24.576 Unavailable Unavailable
192kHz 24.576 Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
For sample rate support of MCLK at 192fs and 384fs, please refer to the pin-compatible WM8761B
device.
LRCIN
BCKIN
DIN
Input Word Length (16 bits)
1/f
LEFT CHANNEL
1
21
1
LSBMSB
16
21
1
RIGHT CHANNEL NO VALID DAT
A
1
Max 4 BCKIN's
LRCIN
BCKIN
DIN
Input Word Length (16 bits)
1/f
LEFT CHANNEL
1
21
1
LSBMSB
1
21
1
RIGHT CHANNEL
NO VALID DAT
A
1
1
max 4 BCKIN's
WM8761 Production Data
w
PD, Rev 4.6, October 2011
15
HARDWARE CONTROL MODES
The WM8761 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
MUTE AND AUTO MUTE OPERATION
Pin 10 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the
automute function, or as an output of the automuted signal.
MUTEB PIN DESCRIPTION
0
Normal Operation, MUTE off
1
Mute DAC channels
Floating
Enable IZD, MUTE becomes an output to indicate when IZD occurs.
Table 2 Mute and Automute Control
Figure 10 Application and Release of MUTE
The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking
MUTE low again allows data into the filter. Refer to Figure 10.
The Infinite Zero Detect (IZD) function detects a series of zero value audio samples of 1024
samples long being applied to both channels. After such an event, a latch is set whose output
(AUTOMUTED) is connected through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is
not being driven, the automute function will assert mute.
If MUTE is tied low, AUTOMUTED is overridden and will not mute. If MUTE is driven from a bi-
directional source, then both MUTE and automute functions are available. If MUTE is not driven,
AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external
mute circuits. AUTOMUTED will be removed as soon as any channel receives a non-zero input.
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0 0.001 0.002 0.003 0.004 0.005 0.006
Time(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

WM8761CBGED/R

Mfr. #:
Buy WM8761CBGED/R
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC
Lifecycle:
New from this manufacturer.
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