.........................DOC #: SP-AP-0021 (Rev AA) Page 4 of 28
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58 VSS_REF GND Ground for outputs.
59 XOUT O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
60 XIN/CLKIN I 14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
61 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to V
IHFS_C
when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
63 SMB_DATA I/O SMBus compatible SDATA.
64 SMB_CLK I SMBus compatible SCLOCK.
64 TSSOP Pin Definition (continued)
Pin No. Name Type Description
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF DOT96 USB
0 0 0 266MHz
100MHz 33MHz 27MHz 14.318MHz 96MHz 48MHz
0 0 1 133MHz
0 1 0 200MHz
0 1 1 166MHz
1 0 0 333MHz
1 0 1 100MHz
1 1 0 400MHz
1 1 1 200MHz
Table 2. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
