UPD5702TU-E2-A

DESCRIPTION
The
µ
PD5702TU is a silicon laterally diffused (LD) MOSFET IC designed for use as power amplifier 1.9 GHz PHS
and 2.4 GHz applications. This IC consists of two stage amplifiers. The device is packaged in surface mount 8 pin
L2MM (Lead Less Mini Mold) plastic package.
FEATURES
Output Power : Pout = +21 dBm MIN. @Pin = 5 dBm, f = 1.9 GHz, VDS = 3.0 V
: P
out = +21 dBm MIN. @Pin = +2 dBm, f = 2.45 GHz, VDS = 3.0 V
Single Supply voltage : V
DS = 3.0 V TYP.
Packaged in 8-pin Lead-Less Minimold (2.0 x 2.2 x 0.5mm) suitable for high-density surface mounting.
APPLICATIONS
1.9 GHz applications (Example : PHS etc.)
2.4 GHz applications (Example : Wireless LAN etc.)
ORDERING INFORMATION (Pb-Free)
Part Number Package Marking Supplying Form
µ
PD5702TU-E2-A
8-pin Lead-Less Minimold
5702 8 mm wide embossed taping
Pin 5, 6, 7, 8 indicates pull-out direction of tape
Qty 5 kpcs/reel
Remark To order evaluation samples, contact your nearby sales office.
Part number for sample order:
µ
PD5702TU-A
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
Document No. PU10455EJ01V0DS (1st edition)
Date Published November 2003 CP(K)
©
NEC Compound Semiconductor Devices 2003
Si LDMOSFET ANALOG RF INTEGRATED CIRCUIT
µ
PD5702TU
3V OPERATION SILICON LDMOSFET RF POWER AMPLIFIER INTEGRATED CIRCUIT
FOR 1.9 GHz PHS AND 2.4 GHz APPLICATIONS
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM
(Top View)
1
2
3
4
8
7
6
5
P
out2
P
out2
GND
P
in1
GND
P
in2
P
in2
P
out1
Q2
Q1
Preliminary Data Sheet PU10455EJ01V0DS
2
µ
PD5702TU
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Test Conditions Ratings Unit
Drain to Source Voltage VDS TA = +25°C 8.0 V
Gate to Source Voltage VGS TA = +25°C 8.0 V
Drain Current of Q1 Ids1 TA = +25°C 45 mA
Drain Current of Q2 Ids2 TA = +25°C 259 mA
Total Power Dissipation PD TA = +85°C Note 4.33 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg 65 to +150 °C
Operating Ambient Temperature TA 40 to +85 °C
Maximum Input Power to Q1 Pin1 TA = +25°C 6 dBm
Maximum Input Power to Q2 Pin2 TA = +25°C 16 dBm
Note Mounted on 33 × 21 mm epoxy glass PWB
RECOMMENDED OPERATING RANGE
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Drain to Source Voltage VDS TA = +25°C 2.7 3.0 3.5 V
Gate to Source Voltage VGS TA = +25°C 0 2.0 2.5 V
Maximum Input Power to Q1 Pin1 VDS = 3V, TA = +25°C 2.0 5.0 dBm
Maximum Input Power to Q2 Pin2 VDS = 3V, TA = +25°C 11.0 15.0 dBm
ELECTRICAL CHARACTERISTICS
(f = 1.9 GHz, V
DS
= 3.0 V, TA = +25°C, unless otherwise specified, using our standard test fixture.)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Gate to Source Voltage VGS 1.0 1.9 2.5 V
Power Added Efficiency PAE
P
in = 5 dBm
P
out = +21.0 dBm
28.0
%
Drain Current
I
DS
Note
155 230 mA
Input Return Loss IRL Pin = 20 dBm
10
dB
Output Return Loss ORL
8
dB
Output Power Pout Pin = 5 dBm 21.0
dBm
Power Gain GP 26.0
dB
Linear Gain GL Pin = 20 dBm
26.5
dB
Adjacent Channel Power Leakage
1
Padj1 Pin = 5 dBm,
600 kHz
60.0 55.0 dBc
Adjacent Channel Power Leakage
2
Padj2 Pin = 5 dBm,
900 kHz
70.0 60 dBc
Occupied Band Width OBW Pin = 5 dBm
250
kHz
Note I
DS is total Drain currents of Q1 and Q2 part.
Preliminary Data Sheet PU10455EJ01V0DS
3
µ
PD5702TU

UPD5702TU-E2-A

Mfr. #:
Manufacturer:
CEL
Description:
IC AMP 802.15.1 2.4GHZ 8MINIMOLD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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