ADM2914-1ARQZ Datasheet ADM2914-1ARQZ, ADM2914-2ARQZ, ADM2914-2ARQZ-RL7 | P10-P12

Data Sheet ADM2914

Rev. F | Page 9 of 16

MONITORING PIN CONNECTIONS

Positive Voltage Monitoring Scheme

When monitoring a positive supply, the desired nominal

operating voltage for monitoring is denoted by V

, I

is the

nominal current through the resistor divider, V

is the

overvoltage trip point, and V

is the undervoltage trip point.

0.5V

UVx

VHx

VLx

OVx

ADM2914

08170-004

Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration

Figure 17 illustrates the positive voltage monitoring input

connection. Three external resistors, R

, R

, and R

, divide the

positive voltage for monitoring, V

, into high-side voltage, V

and low-side voltage, V

. The high-side voltage is connected to

the corresponding VHx pin, and the low-side voltage is

connected to the corresponding VLx pin.

To trigger an overvoltage condition, the low-side voltage (in this

case, V

) must exceed the 0.5 V threshold on the VLx pin. The

low-side voltage, V

, is given by the following equation:

V5.0

















RRR

Also,

RRR 

Therefore, R

, which sets the desired trip point for the

overvoltage monitor, is calculated using the following equation:







)5.0(



(1)

To trigger the undervoltage condition, the high-side voltage,

, must exceed the 0.5 V threshold on the VHx pin. The

high-side voltage, V

, is given by the following equation:

V5.0



















UVPH

RRR

Because R

is already known, R

can be expressed as follows:







MUV

R 

)5.0(

(2)

When R

and R

are known, R

is calculated using the following

equation:







R 

(3)

If V

, I

, V

, or V

changes, each step must be recalculated.

Negative Voltage Monitoring Scheme

Figure 18 shows the circuit configuration for negative supply

voltage monitoring. To monitor the negative voltage, a 1 V

reference voltage is required to connect to the end node of the

voltage divider circuit. This reference voltage is generated

internally and is output through the REF pin.

0.5V

OVx

VHx

VLx

UVx

REF

ADM2914

08170-005

Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration

The equations described in the Positive Voltage Monitoring

Scheme section need some minor modifications for use with

negative voltage monitoring. The 1 V reference voltage is added

to the overall voltage drop; it must therefore be subtracted from

, V

, and V

before using each in the previous equations.

To monitor a negative voltage level, the resistor divider circuit

divides the voltage differential level between the 1 V reference

voltage and the negative supply voltage into high-side voltage,

, and low-side voltage, V

. Similar to the positive voltage

monitoring scheme, the high-side voltage, V

, is connected to

the corresponding VH

pin, and the low-side voltage, V

, is

connected to the corresponding VL

pin. Refer to the Voltage

Monitoring Example section for more information.

ADM2914 Data Sheet

Rev. F | Page 10 of 16

THRESHOLD ACCURACY

The reset threshold accuracy is fundamental, especially at lower

voltage levels. Consider an FPGA application that requires a 1 V

core voltage input with tolerance of ±5%, where the supply has a

specified regulation, for example, ±1.5%. As shown in Figure 19, to

ensure that the supply is within the FPGA input voltage

requirement range, its voltage level must be monitored for UV

and OV conditions. The voltage swing on the supply itself

causes the voltage band available for setting the monitoring

threshold to be quite narrow. In this example, the threshold

voltages, including the tolerances, must fit within a monitor

region of only 0.035 V. The ADM2914 device with 0.1%

resistors can achieve this level of accuracy.

08170-006

1.05V

TIME

OLTAGE

1.015V

1V CORE

VOLTAGE

0.985V

0.95V

+5% TOLERANCE

3.5% RANGE FOR

OV MONITORING

3.5% RANGE FOR

UV MONITORING

+1.5% SUPPLY REGULATION

–1.5% SUPPLY

REGULATION

–5% TOLERANCE

UOTO

Figure 19. Monitoring Threshold Accuracy Example

VOLTAGE MONITORING EXAMPLE

To il lustrate how the ADM2914 device works in a real application,

consider the 1 V input example shown in Figure 19, with the

addition of a −12 V rail.

The first step is to choose the nominal current flow through

both voltage divider circuits, for example, 5 µA.

For the 1 V ±5% input, due to the specified ±1.5% regulation of

the supply, the UV and OV thresholds should be set in the middle

of the voltage monitoring band. In this case, on the ±3.25%

points of the supply, the UV threshold is 0.9675 V and the OV

threshold is 1.0325 V.

Input these values into Equation 1.







k5.96

1050325.1

1)5.0(









Insert the value of R

into Equation 2.







k42.6k5.96

1059675.0

1)5.0(









Then substitute the calculated values for R

and R

into

Equation 3.

k5.96k42.6k5.96

105









This design approach meets the application specifications. As

described previously, the 1 V rail is specified with an input

requirement of ±5% and a supply tolerance of ±1.5%. This

effectively means that the OV threshold of the monitoring

device, including all the tolerance factors, must fit within the

1.015 V to 1.05 V range. Similarly, the UV threshold range must

be between 0.95 V and 0.985 V.

The four worst-case scenarios of minimum and maximum

undervoltage and overvoltage thresholds are calculated as follows:

Minimum overvoltage threshold



V015.1V016.1

)001.1)(500,96(

)999.0)(6420500,96(

14925.0

%1.0

%)1.0(%)1.0(

1%)5.1V5.0(





































MINOV

Maximum overvoltage threshold



V05.1V049.1

%1.0

%)1.0(%)1.0(

1%)5.1V5.0(





















MAXOV

The maximum and minimum overvoltage threshold values lie

within the 1.015 V to 1.05 V range specified. The minimum and

maximum undervoltage thresholds are calculated as follows:

Minimum undervoltage threshold



V95.0V953.0

%1.0%1.0

%)1.0(

1%)5.1V5.0(





















MINUV

Maximum undervoltage threshold



V985.0V984.0

%1.0%1.0

%)1.0(

1%)5.1V5.0(





















MAXUV

Again, these values fit within the specified undervoltage

monitoring range. All four worst-case scenarios satisfy the

tolerance requirement; therefore, the design approach is valid.

ADM2914

VH1

1V RAIL

GND

VL1

VL3

VH3

REF

SEL

–

12V RAIL

2.49MΩ

23.4kΩ

89.8kΩ

96.5kΩ

6.42Ω

96.5kΩ

08170-007

Figure 20. Positive and Negative Supply Monitor Example

Data Sheet ADM2914

Rev. F | Page 11 of 16

Next, consider a −12 V input, which is specified with a ±20%

input. The threshold accuracy required by the supply is chosen

to be within ±5% of the −12 V rail. Therefore, the overvoltage

threshold is set to −13.5 V, and the undervoltage threshold is

−10.5 V. The negative voltage scheme configuration requires

that the 1 V reference voltage be accounted for in Equation 1 to

Equation 3. The 1 V reference voltage is subtracted from V

, and V

, and the absolute value of the result is taken.

Equation 1 becomes







k8.89

10515.13

112)5.0(











Insert the value of R

into Equation 2.







k4.23k8.89

10515.10

112)5.0(











To ca l culate R

, insert the value of R

and R

into Equation 3.





M49.2k4.23k8.89

105

112











POWER-UP AND POWER-DOWN

On power-up, when V

reaches 1 V, the active low

output

is asserted, and the

output pulls up to V

. When the voltage

on the V

pin reaches 1 V, the ADM2914 is guaranteed to assert

low and

high. When V

exceeds 1.9 V (minimum), the

VHx and VLx inputs take control. When V

and each of the

VHx inputs are valid, an internal timer begins. Subsequent to

an adjustable time delay,

weakly pulls high.

UV/OV TIMING CHARACTERISTICS

is an active low output. It is asserted when any of the four

monitored voltages is below its associated threshold. When the

voltage on the V

pin is above 2 V, an internal timer holds

low for an adjustable period, t

UOTO

, after the voltage on all the

monitoring rails rises above their thresholds. This allows time

for all monitored power supplies to stabilize after power-up.

Similarly, any monitored voltage that falls below its threshold

initiates a timer reset, and the timer starts again when all the

monitoring rails rise above their thresholds.

The

and

outputs are held asserted after all faults have

cleared for an adjustable timeout period, determined by the

value of the external capacitor attached to the TIMER pin.

TIMER CAPACITOR SELECTION

The

and

timeout period on the ADM2914 is

programmable via the external timer capacitor, C

TIMER

, placed

between the TIMER pin and ground. The timeout period, t

UOTO

is calculated using the following equation:

F/sec)10)(115)((

9



UOTOTIMER

Refer to Figure 15 in the Typical Performance Characteristics

section, which illustrates the delay time as a function of the

timer capacitor value. A minimum capacitor value of 10 pF is

required. The chosen timer capacitor must have a leakage current

that is less than the 1.3 µA TIMER pin charging current. To

bypass the timeout period, connect the TIMER pin to V

UOD

UOTO

VHx

UOT

VHx

VHx MONITOR TIMING (TIMER PIN TIED TO V

)

Hx MONITOR TIMING

WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,

VHx WILL TRIGGER AN OVERVOLTAGE CONDITION.

08170-024

Figure 21. VHx Positive Voltage Monitoring Timing Diagram

UOD

UOTO

VLx

UOT

VLx

VLx MONITOR TIMING (TIMER PIN TIED TO V

)

Lx MONITOR TIMING

WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,

VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION.

08170-025

Figure 22. VLx Positive Voltage Monitoring Timing Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ADM2914-1ARQZ

Mfr. #:

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Supervisory Circuits Quad UV/OV +/- VTG Supervisor

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