ADM2914 Data Sheet
Rev. F | Page 12 of 16
UV/OV OUTPUT CHARACTERISTICS
Both the
OV
and
UV
outputs have a strong pull-down to
ground and a weak internal pull-up to V
CC
. This permits the pins
to behave as open-drain outputs. When the rise time on the pin
is not critical, the weak pull-up removes the requirement for an
external pull-up resistor. The open-drain configuration allows
for wire-OR’ing of outputs, which is particularly useful when
more than one signal needs to pull down on the output.
At V
CC
= 1 V, a maximum V
OL
= 0.15 V at
UV
is guaranteed. At
V
CC
= 1 V, the weak pull-up current on
OV
is almost turned on.
Consequently, if the state and pull-up strength of the
OV
pin are
important at very low V
CC
, an external pull-up resistor of no more
than 100 kΩ is advised. By adding an external pull-up resistor,
the pull-up strength on the
OV
pin is greater. Therefore, if it is
connected in a wire-ORed configuration, the pull-down strength
of any single device must account for this additional pull-up
strength.
GLITCH IMMUNITY
The ADM2914 is immune to short transients that may occur on
the monitored voltage rails. The device contains internal filtering
circuitry that provides immunity to fast transient glitches. Figure 9
illustrates glitch immunity performance by showing the maximum
transient duration without causing a reset pulse. Glitch immunity
makes the ADM2914 suitable for use in noisy environments.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADM2914 has an undervoltage lockout circuit that monitors
the voltage on the V
CC
pin. When the voltage on V
CC
drops below
1.9 V (minimum), the circuit is activated. The
UV
output is
asserted and the
OV
output is cleared and not allowed to assert.
When V
CC
recovers,
UV
exhibits the same timing characteristics
as if an undervoltage condition had occurred on the inputs.
SHUNT REGULATOR
The ADM2914 is powered via the V
CC
pin. The V
CC
pin can be
directly connected to a voltage rail of up to 6 V. In this mode,
the supply current of the device does not exceed 100 µA. An
internal shunt regulator allows the ADM2914 to operate at
voltage levels greater than 6 V by simply placing a dropper
resistor in series between the supply rail and the V
CC
pin to limit
the input current to less than 10 mA.
Once the supply voltage, V
IN
, has been established, an
appropriate value for the dropper resistor can be calculated.
Begin by determining the maximum supply current required,
I
CCtotal
, by adding the current drawn from the reference and/or
the pull resistors between the outputs and the V
CC
pin to the
maximum specified supply current. The minimum and
maximum shunt regulator voltage specified in Table 1, V
SHUNT min
and V
SHUNT max
, are also required in the following calculations.
Calculate the maximum and minimum dropper resistor values
CCtotal
SHUNT
IN
MAX
I
V
V
R
max
min
A100
min
max
SHUNT
IN
MIN
V
V
R
Based on these values, choose a real-world resistor value within
this range. Then, given the specified accuracy of this resistor,
calculate the minimum and maximum real resistor value
variation, R
REALmin
and R
REALmax
, respectively.
The maximum device power is calculated as follows:
CCtotal
SHUNTmax
CCtotal
REAL
SHUNT
IN
SHUNT
DeviceMax
IV
I
R
VV
VP
min
max
max
max
To check that the calculated value of the resistor will be
acceptable, calculate the maximum device temperature rise.
DeviceMax
JARISEmax
PθTemp
Add this value to the ambient operating temperature. If the
resistor value is acceptable, the result will lie within the
specified operating temperature range of the device, −40°C to
+85°C.
Data Sheet ADM2914
Rev. F | Page 13 of 16
OV LATCH (ADM2914-1)
If an overvoltage condition occurs when the
LATCH
pin is
pulled low, the
OV
pin latches low. Pulling the
LATCH
pin high
clears the latch. If an overvoltage condition clears while the
LATCH
pin is high, the latch is bypassed and the
OV
pin
behaves in the same way as the
UV
pin, with an identical
timeout period. If the
LATCH
pin is pulled low while the
timeout period is active, the
OV
pin latches low, as in normal
operation.
If the
LATCH
pin is kept low during the device power up, a
false positive overvoltage condition is reported by the IC. This
is due to uncertainties between the rising internal reference
voltage and the voltages being monitored and is more evident if
the device is configured for negative voltage monitoring. It is
recommended to add a delay circuit shown in Figure 23 to
temporarily pull the
LATCH
pin high during the device power
up period until the supply and reference voltage stabilize.
VCC
GND
LATCH
C
LATCH
R
LATCH
Figure 23.
LATCH
Pin Delay Circuit
Calculate the component values using the following equation:
LATCH
CC
DELAY
LATCH
R
V
t
C
0.8
ln
where:
V
CC
is the final supply voltage on the VCC pin
t
DELAY
is the estimated delay between VCC pin power up to
LATCH
pin voltage dropping below threshold low voltage.
The exact delay time required, depending on the VCC power up
profile and ramping rate, is always longer than VCC rise time
plus a few milliseconds for margin. Some component value
combinations are shown in Table 6.
Table 6. Standard Component Values of the Latch Delay Circuit
V
CC
(V) t
(DELAY)
(ms) R
LATCH
(kΩ) C
LATCH
(μF)
3.3 10 10.5 0.68
100 105 0.68
5 10 12 0.47
100 120 0.47
6.6 10 10 0.47
100 10 0.47
DISABLE (ADM2914-2)
Pulling the DIS pin high disables both the
UV
and
OV
outputs,
and forces both outputs to remain weakly pulled high, regardless
of any faults that are detected at the inputs. If a UVLO condition
is detected, the
UV
output is asserted and pulls low; however,
the timeout function is bypassed. As soon as the UVLO
condition clears, the
UV
output pulls high. To guarantee
normal operation when the pin is left unconnected, DIS has a
weak 2 μA internal pull-down current.
ADM2914 Data Sheet
Rev. F | Page 14 of 16
TYPICAL APPLICATIONS
VH1
1.8V
1
VL1
VH2
VL2
VH3
VL3
VH4
VL4
SEL
TIMER
UV
OV
LATCH/DIS
REF
GND
V
CC
ADM2914
2.5V
1
3.3V
1
5V
1
SYSTEM
PSU
08170-008
51.7k
3.48k
137k
27.1k
1.82k
111k
174k
11.7k
1M
162k
10.7k
1.5M
NOTES
1
1.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMENT.
Figure 24. Typical Application Diagram for Monitoring 5 V, 3.3 V, 2.5 V, and 1.8 V
VH1
–5V
2
VL1
VL2
VH2
VL3
VH3
VL4
VH4
SEL
TIMER
UV
OV
LATCH/DIS
REF
GND
V
CC
ADM2914
+12V
1
SYSTEM
PSU
08170-009
27.1k
167k
1.96M
1k
83.5k
5.62k
1.98M
NOTES
1
1.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMENT.
2
3% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMENT.
Figure 25. Typical Application Diagram for Monitoring +12 V and −5 V

ADM2914-1ARQZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Quad UV/OV +/- VTG Supervisor
Lifecycle:
New from this manufacturer.
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