ZL30321GGG2 Datasheet ZL30321GGG2, ZL30321GGG | P1-P3

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• Provides synchronous clocks for network interface

cards that support synchronous Ethernet (SyncE)

in addition to telecom interfaces (e.g. T1/E1,

DS3/E3, etc)

• Two independant DPLLs provides timing for the

transmit path (backplane to line rate) and the

receive path (recovered line rate to backplane)

• Supports the requirements of ITU-T G.8262 for

Synchronous Ethernet equipment slave clocks

(EEC option 1 and 2) when combined with a system

synchronizer such as the ZL30116, ZL30121,

ZL30130, ZL30138

• Supports the requirements of Telcordia GR-253

SONET clocks and ITU-T G.813 SDH equipment

slave clocks (SEC)

• Synchronizes to any standard telecom system

reference with a multiple of 8 kHz up to 77.76 MHz

or to Ethernet clock rates including 25 MHz,

50 MHz, 62.5 MHz, and 125 MHz

• Low jitter APLL generates either Ethernet clock

rates (25 MHz, 50 MHz, 62.5 MHz, and 125 MHz)

or SONET/SDH (6.48 MHz, 19.44 MHz,

38.88 MHz, 51.84 MHz, 77.76 MHz) clock rates

• Programmable output synthesizers (P0, P1)

generate clock frequencies with any multiple of

8 kHz up to 100 MHz

• Supports automatic hitless reference switching and

short term holdover during loss of reference inputs

• DPLLs can be configured to provide synchronous

or asynchronous clock outputs

• Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

• Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

Applications

• Carrier Grade Ethernet/SONET/SDH/PDH

Network Interface Cards

• GPON ONT/ONU

• T1/E1 line cards

• DS3/E3 line cards

July 2009

p1_clk0

p1_clk1

p0_clk0

p0_clk1

p0_fp0

p0_fp1

Input

Ports

Ref

Monitors

ref

DPLL 1

apll_clk0

apll_clk1

SPI/I

mode

lock

hold

Synthesizer

APLL

SSI

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

sync0

sync1

sync2

DPLL2

sync

osci

osco

Master

Osc

ZL30321

GbE/SONET/SDH/PDH

Network Interface Synchronizer

Short Form Data Sheet

Ordering Information

ZL30321GGG 100 Pin CABGA Trays

ZL30321GGG2 100 Pin CABGA* Trays

*Pb Free Tin/Silver/Copper in sampling phase

-40

C to +85

ZL30321 Short Form Data Sheet

Zarlink Semiconductor Inc.

Pin Description

100BGA

Pin #

Name

I/O

Type

Description

Input Reference

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

Input References 7:0 (LVCMOS, Schmitt Trigger). These input references

are available to both DPLL1 and DPLL2 for synchronizing output clocks. All

eight input references can lock to any multiple of 8 kHz up to 77.76 MHz

including 25 MHz and 50 MHz. Input ref0 and ref1 have additional

configurable pre-dividers allowing input frequencies such as 62.5 MHz,

125 MHz. These pins are internally pulled up to V

sync0

sync1

sync2

Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt

Trigger). These are optional frame pulse synchronization inputs associated

with input references 0, 1 and 2. These inputs accept frame pulses in a clock

format (50% duty cycle) or a basic frame pulse format with minimum pulse

width of 5 ns. These pins are internally pulled up to V

dd.

Output Clocks and Frame Pulses

D10 apll_clk0 O APLL Output Clock 0 (LVCMOS). Output clock 0 of the APLL. The APLL can

be configured to provide either SONET/SDH or Ethernet clock rates. The

default frequency for this output is 77.76 MHz.

G10 apll_clk1 O APLL Output Clock 1 (LVCMOS). Output clock 1 of the APLL. The APLL can

be configured to provide either SONET/SDH or Ethernet clock rates. The

default frequency for this output is 19.44 MHz.

K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can

be configured to provide any frequency with a multiple of 8 kHz up to

100 MHz, in addition to 2 kHz. The default frequency for this output is

65.536 MHz.

K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a

programmable clock output configurable as a multiple or division of the

p0_clk0 frequency within the range of 2 kHz to 100 MHz. The default

frequency for this output is 32.768 MHz.

K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This

output can be configured to provide virtually any style of output frame pulse

associated with the p0 clocks. The default frequency for this frame pulse

output is 8 kHz.

J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This

output can be configured to provide virtually any style of output frame pulse

associated with the p0 clocks. The default frequency for this frame pulse

output is 8 kHz

J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can

be configured to provide any frequency with a multiple of 8 kHz up to

100 MHz in addition to 2 kHz. The default frequency for this output is

34.368 MHz.

K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a

programmable clock output configurable as a multiple or division of the

p1_clk0 frequency within the range of 2 kHz to 100 MHz. The default

frequency for this output is 68.736 MHz.

ZL30321 Short Form Data Sheet

Zarlink Semiconductor Inc.

E1 ref_out O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of

the output of the reference selector for DPLL2. Switching between input

reference clocks at this output is not hitless.

Control

H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the

device. To ensure proper operation, the device must be reset after power-up.

Reset should be asserted for a minimum of 300 ns.

J5 hs_en I

DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high

at this input enables hitless reference switching. A logic low disables hitless

reference switching and re-aligns DPLL1’s output phase to the phase of the

selected reference input. This feature can also be controlled through software

registers. This pin is internally pulled up to Vdd.

mod0

mod1

DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the

levels on these pins determine the default mode of operation for DPLL1

(Automatic, Normal, Holdover or Freerun). After reset, the mode of operation

can be controlled directly with these pins, or by accessing the dpll1_modesel

Vdd.

Status

H1 lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This

output goes high when DPLL1’s output is frequency and phase locked to the

input reference.

J1 hold O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the

holdover mode.

Serial Interface

E2 sck_scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en =

0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin

acts as the scl pin (bidirectional) for the I

C interface.

F1 si_sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0,

this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin

acts as the sda pin (bidirectional) for the I

C interface.

G1 so O Serial Interface Output (LVCMOS). Serial interface data output. When

i2c_en = 0, this pin acts as the so pin for the serial interface. When i2c_en =

1, this pin is unused and should be left unconnected.

E3 cs_b_asel0 I

Chip Select for SPI/Address Select 0 for I

C (LVCMOS). When i2c_en = 0,

this pin acts as the chip select pin (active low) for the serial interface. When

i2c_en = 1, this pin acts as the asel0 pin for the I

C interface.

F3 asel1 I

Address Select 1 for I

C (LVCMOS). When i2c_en = 1, this pin acts as the

asel1 pin for the I

C interface. Internally pulled up to Vdd. Leave open when

not in use.

F2 asel2 I

Address Select 2 for I

C (LVCMOS). When i2c_en = 1, this pin acts as the

asel2 pin for the I

C interface. Internally pulled up to Vdd. Leave open when

not in use.

100BGA

Pin #

Name

I/O

Type

Description

P1-P3 P4-P6 P7-P9 P10-P10

ZL30321GGG2

Mfr. #:

Buy ZL30321GGG2

Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Pb Free 1GbE PDH Dual DPLL

Lifecycle:

New from this manufacturer.

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ZL30321GGG2

ZL30321GGG2

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