ISL6422EVEZ-T Datasheet NCP6121S52MNR2G, ISL6422EVEZ-T, ISL6422ERZ-T | P10-P12

FN9190.2

August 10, 2007

Functional Description

The ISL6422 dual output voltage regulator makes an ideal

choice for advanced satellite set-top box and personal video

recorder applications. Both supply and control voltage

outputs for two low-noise blocks (LNBs) are available

simultaneously in any output configuration. The device

utilizes built-in DC/DC step up converters that, from a single

supply source ranging from 8V to 14V, generate the voltages

that enable the linear post-regulators to work with a

minimum of dissipated power. An undervoltage lockout

circuit disables the device when VCC drops below a fixed

threshold (7.5V typical).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone of

22kHz in accordance with DiSEqC (EUTELSAT) standards.

No further adjustment is required. The tone oscillator can be

controlled either by the I

C interface (ENT1 or ENT2 bit) or by

a dedicated pin (EXTM1 or EXTM2) that allows immediate

DiSEqC data encoding separately for each LNB. All the

functions of this IC are controlled via the I

C bus by writing to

the system registers. The same registers can be read back,

and four bits will report the diagnostic status. The internal

oscillator operates the converters at twenty times the 22k tone

frequency. The device offers full I

C compatibility and

supports 2.5V, 3.3V or 5V logic, and up to 400kHz operation.

If the Tone Enable bits (ENT1 and ENT2) are set LOW and

the MSEL1 and MSEL2 bits set LOW through I

C, then the

EXTM1 and EXTM2 terminal activates the internal tone

signal, modulating the DC output with a 680mV

P-P

typ

symmetrical tone waveform. The presence of this signal

usually provides the LNB with information about the band to

be received.

Burst coding of the tone can be accomplished due to the fast

response of the EXTM1 and EXTM2 input and rapid tone

response. This allows implementation of the DiSEqC

(EUTELSAT) protocols.

When the ENT1 or ENT2 bit is set HIGH, a continuous

22kHz tone is generated regardless of the EXTM1 and

EXTM2 pin logic status for the corresponding regulator

channel (LNB-A or LNB-B). The ENT1 or ENT2 bit must be

set LOW when the EXTM1 and/or EXTM2 pin is used for

DiSEqC encoding.

The EXTM1 and EXTM2 pins also accept an externally

modulated tone command when the MSEL1 or MSEL2 I

bit is set high.

DiSEqC Decoder

TDIN1 and TDIN2 are the inputs to the tone decoders of

Channels 1 and 2 respectively. They accept the tone signal

derived from the V

OUT

through the 10nF decoupling

capacitor. The detector threshold can be set to 200mV

maximum in the Receive mode and to 400mV minimum in

the Transmit mode by means of the logic presented to the

TXT1 or TXT2 pin. If tone is detected, the open drain pin

TDOUT1 or TDOUT2 is asserted low. This also enables the

tone diagnostics to be performed, apart from the normal tone

detection function.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.75µF. In order to minimize the power

dissipation, the output voltage of the internal step-up

converter is adjusted to allow the linear regulator to work at

minimum dropout.

When the device is put in the shutdown mode (EN1 and

EN2 = LOW), both PWM power blocks are disabled (that is,

when EN1 = 0, PWM1 is disabled, and when EN2 = 0,

PWM2 is disabled).

When the regulator blocks are active (EN1 and EN2 = HIGH,

and VSPEN1 and VSPEN2 = LOW), the output can be

controlled via I

C logic to be between 13V and 14V or

between 18V and 19V (typical) by means of the Voltage

Select bits (VTOP1, VTOP2, VBOT1, and VBOT2) for

remote controlling of non-DiSEqC LNBs.

When the regulator blocks are active (EN1 and EN2 = HIGH,

and VSPEN1 and VSPEN2 = HIGH), the VBOT1 and

VBOT2 bits and the SELVTOP1 and SELVTOP2 pins will

control the output between 13V and 14V and the VTOP1 and

VTOP2 and the SELVTOP1 and SELVTOP2 pins will control

the output between 18V and 19V.

Output Timing

The output voltage rise and fall times can be set by an the

external capacitor on the TCAP1 and TCAP2 pins. The

output rise and fall times is given by Equation 1:

where:

• C is the TCAP value in nF

• t is the required slew rate in ms, and

• ΔV is the differential transition voltage from low output

voltage range to the high output range in Volts.

Rise and fall time will typically be the same.

The maximum recommended value for TCAP1 and TCAP2

would be the base on the maximum transition time allowed

in the system application. Too small a value of TCAP1 and

TCAP2 can cause high peak currents in the boost circuit. For

example, a 10V/ms slew on a 80µF VSW capacitor with an

inductor of 15µH can cause a peak inductor current of

approximately 2.3A.

270()t

ΔV

---------------- -

(EQ. 1)

ISL6422

FN9190.2

August 10, 2007

Current Limiting

The dynamic back current limit block has five thresholds that

can be selected by the following bits of the SR.

• ISEL1H and ISEL2H

• ISEL1L and ISEL2L

• ISEL1R and ISEL2R

See Table 8 and Table 9 for threshold selection using these

bits. The DCL1 and DCL2 bits have to be set to low for this

mode of operation. In this mode, the overcurrent protection

circuit works dynamically 23µs after an overload is detected,

and the output is shutdown for a time t

OFF

, typically 900ms.

Simultaneously, the OLF1 or OLF2 bit of the System

output is resumed for a time t

= 20ms. During t

, the

device output will be current limited to a 990mA typ level. If

the overload is still detected, the protection circuit will cycle

again through t

OFF

and t

. At the end of a full t

, in which

no overload is detected, normal operation is resumed and

the OLF1 or OLF2 bit is reset to LOW. Typical t

OFF

time is 920ms as determined by an internal timer. This

dynamic operation can greatly reduce the power dissipation

in a short circuit condition, still ensuring excellent power-on

start-up in most conditions.

However, there could be some cases in which a highly

capacitive load on the output may cause a difficult start-up

when the dynamic protection is chosen. This can be solved

by initiating any power start-up in static mode (DCL = HIGH)

and then switching to the dynamic mode (DCL = LOW) after

a chosen amount of time. When in static mode, the OLF1 or

OLF2 bit goes HIGH when the peak current sense threshold

is reached and returns LOW when the overload condition is

cleared. The OLF1, OLF2, BCF1, and BCF2 bits will be LOW

at the end of initial power-on soft-start. In the static mode the

output current through the linears is limited to 990mA typ.

When a 19.3V line is connected onto a VOUT1 or VOUT2

pin that has been set to 13.3V, the linear will then enter a

dynamic back current limit state. When a dynamic back

current limit of greater that 125mA typ is sensed at the lower

FET of the linear for a period greater that 100µs, the output

is disabled for a period of 5ms and the BCF1 and BCF2 bits

are set. If the 19.3V remains connected, the output will cycle

through the ON = 100µs/OFF = 5ms. The output will recover

when the fault is removed.

Thermal Protection

This IC is protected against overheating. When the junction

temperature exceeds +150°C (typical), the step-up converter

and the linear regulator are shut off and the OTF bit of the

SR is set HIGH. Normal operation is resumed and the OTF

bit is reset LOW when the junction is cooled down to +130°C

(typical).

The FLT

pin serves as an interrupt for the processor when

an over temperature, overcurrent or backwards overcurrent

fault is detected by the LNB controller or when both channels

are disabled by the I

C EN1 and EN2 bits being set low.

Should the I

C lose power (for example by shorting BYP pin

to ground), it is designed to power up with all control bits set

to 0 (particularly the EN1 and EN2 bits). This prevents the

device from coming back up in a state not desired by the

host controller. If the host controller sees a FLT

low, it

should read the I

C bits and find both EN1 and EN2 bits low.

When it desires one or both to be high, it should re-write the

C to the desired state.

External Output Voltage Selection

The output voltage can be selected by the I

C bus.

Additionally, the package offers two pins (SELVTOP1 and

SELVTOP2) for independent 13 through 19V output voltage

selection.

C Bus Interface for ISL6422

(Refer to Phillips I

C Specification, Rev. 2.1)

Data transmission from the main microprocessor to the

ISL6422 and vice versa takes place through the two-wire I

bus interface, consisting of the two lines SDA and SCL. Both

SDA and SCL are bidirectional lines. They are connected to a

positive supply voltage via a pull-up resistor. (Pull-up resistors

to positive supply voltage must be externally connected). When

the bus is free, both lines are HIGH. The output stages of

ISL6422 will have an open drain/open collector in order to

perform the wired-AND function. Data on the I

C bus can be

transferred up to 100kbps in the standard mode or up to

400kbps in the fast mode. The level of logic “0” and logic “1”

depends on the value of V

as per the “Electrical

Specifications” table on page 5. One clock pulse is generated

for each data bit transferred.

TABLE 1.

VSPEN1,

VSPEN2

VTOP1,

VTOP2

VBOT1,

VBOT2

SELVTOP1,

SELVTOP2

VOUT1,

VOUT12

0 X 0 0 13.3V

0 X 1 0 14.3V

0 0 X 1 18.3V

0 1 X 1 19.3V

1 0 0 X 13.3V

1 0 1 X 14.3V

1 1 0 X 18.3V

1 1 1 X 19.3V

ISL6422

FN9190.2

August 10, 2007

Data Validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can change only when the clock signal on the SCL line is

LOW. Refer to Figure 4.

START and STOP Conditions

As shown in Figure 5, the START condition is a HIGH to

LOW transition of the SDA line while SCL is HIGH.

The STOP condition is a LOW to HIGH transition on the SDA

line while SCL is HIGH. A STOP condition must be sent

before each START condition.

Byte Format

Every byte put on the SDA line must be eight bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most significant

bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on

the SDA line during the acknowledge clock pulse (see

Figure 6). The peripheral that acknowledges has to pull

down (LOW) the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during this clock

pulse. (Set-up and hold times must also be taken into

account).

The peripheral which has been addressed has to generate

an acknowledge after the reception of each byte, otherwise

the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

The ISL6422 will not generate the acknowledge if the

POWER OK signal from the UVLO is LOW.

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the

microprocessor can use a simpler transmission; it waits one

clock pulse without checking the slave acknowledging and

sends the new data. Although, this approach is less

protected from error and decreases the noise immunity.

ISL6422 Software Description

Interface Protocol

The interface protocol is comprised of the following, as

shown in Table 2:

• Start condition (S)

• Chip address byte (MSB on left; the LSB bit determines

read (1) or write (0) transmission) (the assigned I

C slave

address for the ISL6422 is 0001 00XX)

• Sequence of data (1 byte + Acknowledge)

• Stop condition (P)

System Register Format

• R, W = Read and Write bit

• R = Read-only bit

• X = Unused

All bits reset to 0 at Power-On

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

FIGURE 4. DATA VALIDITY

SDA

SCL

START

CONDITION

FIGURE 5. START AND STOP WAVEFORMS

STOP

CONDITION

TABLE 2. INTERFACE PROTOCOL

S0001000R/WACK Data (8 bits) ACKP

TABLE 3. STATUS REGISTER 1 (SR1)

R, W R, W R, W R R R R R

SR1H SR1M SR1L OTF CABF1 OUVF1 OLF1 BCF1

TABLE 4. TONE REGISTER 2 (SR2)

R, W R, W R, W R, W R, W R, W R, W R, W

SR2H SR2M SR2L ENT1 MSEL1 TTH1 X X

TABLE 5. COMMAND REGISTER 3 (SR3)

R, W R, W R, W R, W R, W R, W R, W R, W

SR3H SR3M SR3L DCL1 VSPEN1 ISEL1R

ISEL1H ISEL1L

SDA

SCL

FIGURE 6. ACKNOWLEDGE ON THE I

C BUS

ACKNOWLEDGE

FROM SLAVE

MSB

START

ISL6422

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ISL6422EVEZ-T

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