9
FN9190.2
August 10, 2007
Functional Pin Descriptions
SYMBOL FUNCTION
SDA Bidirectional data from/to I
2
C bus.
SCL Clock from I
2
C bus.
VSW1 and VSW2 Input of the linear post-regulator.
PGND1 and PGND2 Dedicated ground for the output gate driver of respective PWM.
CS1 and CS2 Current sense input; connect the sense resistor Rsc at this pin for desired overcurrent value for respective PWM.
SGND Small signal ground for the IC.
TCAP1 and TCAP2 Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.22µF.
BYP Bypass capacitor for internal 5V.
TXT1 and TXT2 TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV
max for the Rx mode when the TXT1 and TXT2 are set low. The threshold is 400mV min in the Tx mode when TXT1
and TXT2 are set high. If Tx/Rx mode is set by I
2
C bit TTH(1 ,2), when TTH(1, 2) = 1, then TXT(1, 2) will be driven high
(5V) by an on-chip driver.
VCC Main power supply to the chip.
GATE1 and GATE2 These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of
driving the gate of a power FET. These outputs are actively held low when V
CC
is below the UVLO threshold.
VOUT1 and VOUT2 Output voltage for LNB A and LNB B respectively.
ADDR0 and ADDR1 Address pins select four different device addresses per Table 19.
EXTM1 and EXTM2 These pins can be used in two ways:
1. As an input for externally modulated DiSEqC tone signal that is transferred symmetrically onto V
OUT
.
2. Alternatively apply a DiSEqC modulation envelope that modulates an internal tone and then transfers it symmetrically
onto V
OUT
.
FLT This is an open drain output from the controller. When the FLT goes low, it indicates that an Over-Temperature has
occurred. The processor should then look at the I
2
C register to get the actual cause of the error. A high on the FLT
indicates that the device is functioning normally.
CPVOUT, CPSWIN,
CPSWOUT
A 47nF charge pump cap is connected to CPVOUT. Connect a 1.5nF capacitor between CPSWIN and CPSWOUT.
SELVTOP1 and
SELVTOP2
The following description applies to both pins and both bits.
When this pin is low, the V
OUT
is in the 13V/14V range selected by the I
2
C bit VBOT1 and VBOT2.
When this pin is high, the 18V/19V range is selected by the I
2
C bit VTOP1 and VTOP2.
The voltage select pin voltage VSPEN1 and VSPEN2 I
2
C bit must be set low for the SELVTOP1 and SELVTOP2 pins
to be active. Setting VSPEN1 and VSPEN2 high disables these pins and voltage selection will be done using the I
2
C
bits VBOT1 and VBOT2 and VTOP1 and VTOP2 only.
TDIN1 and TDIN2
TDOUT1 and TDOUT2
TDIN1 and TDIN2 are the tone decoder inputs for Channels 1 and 2.
TDOUT1 and TDOUT2 are the tone detector outputs for Channels 1 and 2. TDOUT1 and TDOUT2 are open drain outputs.
AGND Analog ground for the IC.
ISL6422
