MC74LVXT4052
http://onsemi.com
9
Figure 12. Break−Before−Make, Test Set−Up Figure 13. Break−Before−Make Time
ON
OFF
6
7
8
V
CC
V
EE
9−11
Tek 11801B
DSO
COM INPUT
16
R
L
C
L
V
IN
50
V
IN
80%
V
CC
t
BBM
80% of
V
OH
Figure 14. Propagation Delays, Channel Select
to Analog Out
Figure 15. Propagation Delay, Test Set−Up
Channel Select to Analog Out
V
CC
GND
CHANNEL
SELECT
ANALOG
OUT
50%
t
PLH
t
PHL
50%
ON/OFF
6
7
8
16
V
CC
C
L
*
CHANNEL SELECT
TEST
POINT
COMMON
OFF/ON
ANALOG I/O
V
CC
ON/OFF
6
7
8
ENABLE
V
CC
ENABLE
90%
50%
10%
t
f
t
r
V
CC
GND
ANALOG
OUT
t
PZL
ANALOG
OUT
t
PZH
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
10%
90%
t
PLZ
t
PHZ
50%
50%
ANALOG I/O
C
L
*
TEST
POINT
16
V
CC
1 K
1
2
1
2
POSITION 1 WHEN TESTING t
PHZ
AND t
PZH
POSITION 2 WHEN TESTING t
PLZ
AND t
PZL
GND
GND
O/I
Channel Selects connected
to V
IN
and appropriately
configured to test each switch.
V
OH
*Includes all probe and jig capacitance.
Figure 16. Propagation Delays, Enable to
Analog Out
Figure 17. Propagation Delay, Test Set−Up
Enable to Analog Out
