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MC14007UBD
P1-P3
P4-P6
P7-P7
MC14007UB
http://onsemi.com
4
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25
°
C)
Symbol
Characteristic
V
DD
Vdc
Min
Ty
p
(Note 6)
Max
Unit
t
TLH
Output Rise T
ime
t
TLH
= (1.2 ns/pF) C
L
+ 30 ns
t
TLH
= (0.5 ns/pF) C
L
+ 20 ns
t
TLH
= (0.4 ns/pF) C
L
+ 15 ns
5.0
10
15
−
−
−
90
45
35
180
90
70
ns
t
THL
Output Fall T
ime
t
THL
= (1.2 ns/pF) C
L
+ 15 ns
t
THL
= (0.5 ns/pF) C
L
+ 15 ns
t
THL
= (0.4 ns/pF) C
L
+ 10 ns
5.0
10
15
−
−
−
75
40
30
150
80
60
ns
t
PLH
T
urn−Of
f Delay Time
t
PLH
= (1.5 ns/pF) C
L
+ 35 ns
t
PLH
= (0.2 ns/pF) C
L
+ 20 ns
t
PLH
= (0.15 ns/pF) C
L
+ 17.5 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
ns
t
PHL
T
urn−On Delay Time
t
PHL
= (1.0 ns/pF) C
L
+ 10 ns
t
PHL
= (0.3 ns/pF) C
L
+ 15 ns
t
PHL
= (0.2 ns/pF) C
L
+ 15 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
ns
5.
The formulas given are for the typical characteristics only
. Switching specifications are for device connected as an inverter
.
6.
Data labelled “T
yp” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 3. T
ypical Output Source Characteristics
Figure 4. T
ypical Output Sink Characteristics
V
DD
= -V
GS
V
DD
= V
GS
14
14
V
DS
= V
OH
- V
DD
V
DS
= V
OL
V
SS
V
SS
7
7
I
OH
I
OL
I
OH
, DRAIN CURRENT (mAdc)
I
OL
, DRAIN CURRENT (mAdc)
0
-4.0
-8.0
-12
-16
-20
-8.0
-10
-6.0
-4.0
-2.0
-0
V
DS
, DRAIN VOL
T
AGE (Vdc)
20
16
12
8.0
4.0
0
0
2.0
4.0
6.0
8.0
10
V
DS
, DRAIN VOL
T
AGE (Vdc)
T
A
= -55
°
C
T
A
= +25
°
C
T
A
= +125
°
C
a
b
c
V
GS
= -5.0 Vdc
b
c
a
-10 Vdc
-15 Vdc
c
b
c
b
a
a
a
b
c
a
b
c
a
b
c
5.0 Vdc
T
A
= -55
°
C
T
A
= +25
°
C
T
A
= +125
°
C
a
b
c
V
GS
= 15 Vdc
10 Vdc
All unused inputs connected to ground.
All unused inputs connected to ground.
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
MC14007UB
http://onsemi.com
5
Figure 5. Switching Time and Power Dissipation T
est Circuit and W
aveforms
PULSE
GENERA
TOR
V
DD
500
m
F
0.01
m
F
CERAMIC
14
C
L
V
out
V
SS
7
V
in
I
D
V
in
V
out
90%
50%
10%
90%
50%
10%
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
t
THL
t
TLH
t
PHL
t
PLH
APPLICA
TIONS
The
MC14007UB dual pair plus inverter
, which has access to
all its elements offers a
number of unique circuit applications.
Figures 1, 6, and 7 are a few examples of the device flexibility
.
Figure 6. 3−State Buffer
+V
DD
DISABLE3
INPUT10
DISABLE
6
12OUTPUT
11
1
2
9
8
7
INPUT
DISABLE
OUTPUT
1
0
X
0
0
1
0
1
OPEN
X = Don’t Care
Figure 7. AOI Functions Using T
ree Logic
V
DD
14
13
11
10
3
6
B
C
A
9
5
4
8
7
1
2
OUTPUT
OUT = A+B
•
C
Substrates
of P−Channel devices internally connected to V
DD
;
Substrates of N−Channel devices internally connected to
V
SS
.
12
MC14007UB
http://onsemi.com
6
ORDERING INFORMA
TION
Device
Package
Shipping
†
MC14007UBDG
SOIC−14
(Pb−Free)
55 Units / Rail
MC14007UBDR2G
SOIC−14
(Pb−Free)
2500 / T
ape & Reel
NL
V14007UBDR2G*
SOIC−14
(Pb−Free)
2500 / T
ape & Reel
†
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
ape and Reel
Packaging
Specifications Brochure, BRD801
1/D.
*NL
V
Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PP
AP
Capable.
P1-P3
P4-P6
P7-P7
MC14007UBD
Mfr. #:
Buy MC14007UBD
Manufacturer:
ON Semiconductor
Description:
IC COMP DUAL PAIR W/INV 14-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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EMS
Payment:
T/T
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