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NB6L11SMNG

P1-P3P4-P6P7-P9P10-P11
NB6L11S
www.onsemi.com
4
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS V
CC
= 2.375 V to 2.625 V, GND = 0 V,
T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
I
CC
Power Supply Current (Note 8) 30 45 mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 15, 16, 20, and 22)
V
th
Input Threshold Reference Voltage Range (Note 7) GND +100 V
CC
− 100 mV
V
IH
Single−ended Input HIGH Voltage V
th
+ 100 V
CC
mV
V
IL
Single−ended Input LOW Voltage GND V
th
− 100 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 12, 13, 14, 21, and 23)
V
IHD
Differential Input HIGH Voltage 100 V
CC
mV
V
ILD
Differential Input LOW Voltage GND V
CC
− 100 mV
V
CMR
Input Common Mode Range (Differential Configuration) GND + 50 V
CC
− 50 mV
V
ID
Differential Input Voltage (V
IHD
− V
ILD
) 100 V
CC
− GND mV
R
TIN
Internal Input Termination Resistor 40 50 60
W
LVDS OUTPUTS (Note 4)
V
OD
Differential Output Voltage 250 450 mV
DV
OD
Change in Magnitude of V
OD
for Complementary Output States (Note 9) 0 1 25 mV
V
OS
Offset Voltage (Figure 19) 1125 1375 mV
DV
OS
Change in Magnitude of V
OS
for Complementary Output States (Note 9) 0 1 25 mV
V
OH
Output HIGH Voltage (Note 5) 1425 1600 mV
V
OL
Output LOW Voltage (Note 6) 900 1075 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 18.
5. V
OH
max = V
OS
max + ½ V
OD
max.
6. V
OL
max = V
OS
min − ½ V
OD
max.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, D/D
at the DC level within V
CMR
and output pins loaded with R
L
= 100 W across differential.
9. Parameter guaranteed by design verification not tested in production.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NB6L11S
www.onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 2.375 V to 2.625 V, GND = 0 V; (Note 10)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)f
in
≤ 1.0 GHz
(Figure 4) f
in
= 1.5 GHz
f
in
= 2.0 GHz
220
200
170
350
300
270
220
200
170
350
300
270
220
200
170
350
300
270
mV
f
DATA
Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s
t
PLH
,
t
PHL
Differential Input to Differential Output
Propagation Delay
250 450 250 380 450 250 450 ps
t
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
t
JITTER
RMS Random Clock Jitter (Note 13) f
in
= 1.0 GHz
f
in
= 1.5 GHz
Peak−to−Peak Data Dependent Jitter (Note 14)
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
0.5
0.5
6
7
10
0.5
0.5
6
7
10
0.5
0.5
6
7
10
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100 V
CC
−
GND
100 V
CC
−
GND
100 V
CC
−
GND
mV
t
r
t
f
Output Rise/Fall Times @ 250 MHz Q, Q
(20% − 80%)
70 120 170 70 120 170 70 120 170 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
− 1400 mV offset. All loading with an external R
L
= 100 W across
“D” and “D
” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 17 differential measurement of t
skew
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
12.Input voltage swing is a single−ended measurement operating in differential mode.
13.RMS jitter with 50% Duty Cycle input clock signal.
14.Deterministic jitter with input NRZ data at PRBS 2
23
−1 and K28.5.
15.Skew is measured between outputs under identical transition @ 250 MHz.
16.The worst case condition between Q0/Q0
and Q1/Q1 from D, D, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 2.5 V)
OUTPUT VOLTAGE AMPLITUDE (mV)
0
50
100
150
200
250
300
350
400
0.5 1 1.5 2 2.5 30
85°C
−40°C
25°C
NB6L11S
www.onsemi.com
6
Figure 5. Typical Phase Noise Plot at
f
carrier
= 622.08 MHz
Figure 6. Typical Phase Noise Plot at
f
carrier
= 1 GHz
Figure 7. Typical Phase Noise Plot at
f
carrier
= 1.5 GHz
Figure 8. Typical Phase Noise Plot at
f
carrier
= 2 GHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the NB6L11S device
at frequencies 622.08 MHz, 1 GHz, 1.5 GHz and 2 GHz
respectively at an operating voltage of 2.5 V in room
temperature. The RMS Phase Jitter contributed by the
device (integrated between 12 kHz and 20 MHz; as shown
in the shaded region of the plot) at each of the frequencies
is 40 fs, 22 fs, 14 fs and 12 fs respectively. The input source
used for the phase noise measurements is Agilent E8663B.
P1-P3P4-P6P7-P9P10-P11

NB6L11SMNG

Mfr. #:
Buy NB6L11SMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer HF LVDS FANOUT BUFF/ TRANS
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New from this manufacturer.
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