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MC100LVEP05DTR2G

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 2
1 Publication Order Number:
MC100LVEP05/D
MC100LVEP05
2.5V / 3.3V ECL 2-Input
Differential AND/NAND
Description
The MC100LVEP05 is a 2−input differential AND/NAND gate.
The MC100LVEP05 is the low voltage version of the MC100EP05
and is functionally equivalent to the EL05 and LVEL05 devices. With
AC performance much faster than the LVEL05 device, the
MC100LVEP05 is ideal for low voltage applications requiring the
fastest AC performance available.
The 100 Series contains temperature compensation.
Features
• 220 ps Typical Propagation Delay
• Input Clock Frequency > 3 GHz
• 0.2 ps Typical RMS Random Clock Period Jitter
• LVPECL Mode Operating Range: V
CC
= 2.375 V to 3.6 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −2.375 V to −3.6 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Y = Year
W = Work Week
G = Pb−Free Package
K = MC100
M = Date Code
A = Assembly Location
L = Wafer Lot
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
G
KU05
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
DFN8
MN SUFFIX
CASE 506AA
4
(Note: Microdot may be in either location)
6N MG
G
1
1
8
KVP05
AYWWG
G
1
8
SOIC−8
D SUFFIX
CASE 751
MC100LVEP05
http://onsemi.com
2
F
igure 1. 8−Lead Pinout (Top View) and Logic
Diagram
1
2
3
45
6
7
8
Q
V
EE
V
CC
D
0
QD
1
D
1
D
0
Table 1. PIN DESCRIPTION
Pin Function
D0*, D1*, D0**, D1** ECL Data Inputs
Q, Q ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
* Pins will default LOW when left open.
** Pins will default to V
CC
/2when left open.
Table 2. TRUTH TABLE
D0 D1 D0 D1 Q Q
L
L
H
H
L
H
L
H
H
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−8
DFN8
Pb Pkg
Level 1
Level 1
Pb−Free Pkg
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100LVEP05
http://onsemi.com
3
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6
−6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 100EP DC CHARACTERISTICS, PECL V
CC
= 2.5 V, V
EE
= 0 V (Note 3)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 15 25 32 17 27 36 19 28 38 mA
V
OH
Output HIGH Voltage (Note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
V
OL
Output LOW Voltage (Note 4) 555 730 900 555 730 900 555 730 900 mV
V
IH
Input HIGH Voltage (Single−Ended) 1355 1620 1355 1620 1355 1620 mV
V
IL
Input LOW Voltage (Single−Ended) 555 900 555 900 555 900 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Notes 5, 6)
1.2 2.5 1.2 2.5 1.2 2.5 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current D
D
0.5
−150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to −1.3 V.
4. All loading with 50 W to V
CC
− 2.0 V.
5. Single−ended input CLK pin operation is limited to V
CC
3.0 V in PECL mode.
6. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
P1-P3P4-P6P7-P9P10-P10

MC100LVEP05DTR2G

Mfr. #:
Buy MC100LVEP05DTR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2 INPUT DIFFERENTIAL AND NAND
Lifecycle:
New from this manufacturer.
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