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Table 17. ANALOG CONTROL REGISTER 0 PARAMETERS
Parameter Value Description Info
V20VEN
0 Disable
Enables/disables the V20V regulator p 19
1 Enable
DC2EN
0 Disable
Enables/disables the DC2 converter p 19
1 Enable
XCLKEN
0 Disable
Enables/disables the XCLK output signal p 19
1 Enable
TRIGEN
0 Disable
TRIG/ARXD pin outputs the Tx activity monitor signal when enabled.
When disabled the TRIG/ARXD pin is tri−state.
p 19
1 Enable
V20VCLIMIT 000 − 111
Adjustment of the V20V current limit as configured by R
6
by DI
20V,
STEP
per bit
p 19
Remark: Bit 7 is reserved.
Analog Control Register 1
The Analog Control Register 1 is located at address 0x02 and can be used to configure the voltage monitors.
Table 18. ANALOG CONTROL REGISTER 1
Analog Control Register 1 (AnaCtrl1)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 0 0 0 0 0
Data
V20V_OK_M VDD2_OK_M VFILT_OK_M ANAOUTCTRL
-
Table 19. ANALOG CONTROL REGISTER 1 PARAMETERS
Parameter Value Description Info
V20V_OK_M
0 Enable
Enable to include the voltage monitor output in the SAVEB calculation. p 19
1 Disable
VDD2_OK_M
0 Enable
Enable to include the voltage monitor output in the SAVEB calculation. p 19
1 Disable
VFILT_OK_M
0 Enable
Enable to include the voltage monitor output in the SAVEB calculation. p 18
1 Disable
ANAOUTCTR
L
000 Disable Analog output is disabled
p 23
001 Enable Analog output monitors VBUS1
010 Enable Analog output monitors VFILT
011 Enable Analog output monitors V20V
100 Enable Analog output monitors VDD2
101 Enable Analog output monitors VDDA
110 Enable Analog output monitors Bus current
111 Enable Analog output monitors Temperature
Remark: Bit 0 and bit 7 are reserved.
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Analog Status Register
The Analog Status Register is located at address 0x03 and can be used to verify the voltage monitors, Xtal and thermal status.
Table 20. ANALOG STATUS REGISTER
Analog Status Register (AnaStat)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x03
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Data V20V VDD2 VBUS VFILT XTAL TW TSD
Table 21. ANALOG STATUS REGISTER PARAMETERS
Parameter Value Value Description Info
V20V
0 nOK
‘1’ if voltage on V20V-pin is above the V20V undervoltage level p 19
1 OK
VDD2
0 nOK
‘1’ if voltage on VDD2-pin is above the VDD2 undervoltage level p 19
1 OK
VBUS
0 nOK
‘1’ if bus voltage is above the VBUS undervoltage level P 18
1 OK
VFILT
0 nOK
‘1’ if voltage on VFILT-pin is above the VFILT undervoltage level p 18
1 OK
XTAL
0 nOK
‘1’ if XTAL is up and running p 19
1 OK
TW
0 No TW
‘1’ if Thermal Warning detected
p 22
1 TW
TSD
0 No TSD
Contains information about the previous Thermal Shutdown situation
1 TSD
Remark: Bit 7 is reserved.
Revision ID register
The Revision ID register is located at address 0x05 and can be read out to check the revision ID of the silicon and by the
firmwire of the host controller to determine the part number of the transceiver
Table 22. REVISION ID REGISTER
Revision ID Register (RevID)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x05
Access R R R R R R R R
Reset X X X 0 1 1 0 0
Data Revision Part Number
Table 23. REVISION ID REGISTER PARAMETERS
Parameter Value Value Description Info
Revision Silicon revision ID
Part Number 01100 NCN5130 Transceiver Part Number
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PACKAGE THERMAL CHARACTERISTICS
The NCN5130 is available in a QFN40 package. For cooling optimizations, the QFN40 has an exposed thermal pad which
has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer.
Figure 58 gives an example of good heat transfer. The exposed thermal pad is soldered directly on the top ground layer (left
picture of Figure 58). It‘s advised to make the top ground layer as large as possible (see arrows Figure 58). To improve the heat
transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of
Figure 58). It‘s advised to make this bottom ground layer as large as possible and with as less as possible interruptions.
For precise thermal cooling calculations the major thermal resistances of the device are given (Table 4). The thermal media
to which the power of the devices has to be given are:
Static environmental air (via the case)
PCB board copper area (via the exposed pad)
The major thermal resistances of the device are the Rth from the junction to the ambient (Rth
ja
) and the overall Rth from
the junction to exposed pad (Rth
jp
). In Table 4 one can find the values for the Rth
ja
and Rth
jp
, simulated according to JESD−51.
The Rth
ja
for 2S2P is simulated conform JEDEC JESD−51 as follows:
A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used
Board thickness is 1.46 mm (FR4 PCB material)
The 2 signal layers: 70 mm thick copper with an area of 5500 mm
2
copper and 20% conductivity
The 2 power internal planes: 36 mm thick copper with an area of 5500 mm
2
copper and 90% conductivity
The Rth
ja
for 1S0P is simulated conform to JEDEC JESD−51 as follows:
A 1−layer printed circuit board with only 1 layer
Board thickness is 1.46 mm (FR4 PCB material)
The layer has a thickness of 70 mm copper with an area of 5500 mm
2
copper and 20% conductivity
Figure 58. PCB Ground Plane Layout Condition (left picture displays the top ground layer, right picture displays
the bottom ground layer)
ORDERING INFORMATION
Device Number Temperature Range Package Shipping
NCN5130MNG −40°C to 105°C QFN−40
(Pb−Free)
50 Units / Tube
100 Tubes / Box
NCN5130MNTWG −40°C to 105°C QFN−40
(Pb−Free)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.

NCN5130MNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Communication ICs - Various KNXB FULL FEATURE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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