÷4/÷5 Differential-to-3.3V LVPECL
Clock Generator
87354
DATASHEET
87354 REVISION A 2/12/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 87354 is a high performance ÷4/÷5
Differential-to-3.3V LVPECL Clock Generator. The CLK, nCLK pair can ac-
cept most standard differential input levels.The 87354 is characterized to
operate from a 3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the 87354 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
FEATURES
One differential 3.3V LVPECL output
One CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum clock input frequency: 1GHz
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.1ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 3.0V to 3.465V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free RoHS compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
87354
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
CLK
nCLK
MR
F_SEL
1
2
3
4
Vcc
Q
nQ
V
EE
8
7
6
5
Q
nQ
CLK
nCLK
÷4
MR
÷5
R
0
1
F_SEL
÷4/÷5 DIFFERENTIAL-TO-
3.3V LVPECL CLOCK GENERATOR
87354 DATA SHEET
2 REVISION A 2/12/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output (Q) to go low and the inverted output (nQ)
to go high. When logic LOW, the internal dividers and the output are
enabled. LVCMOS / LVTTL interface levels. See Table 3.
4 F_SEL Input Pulldown
Selects divider value for Q, nQ outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
5V
EE
Power Negative supply pin.
6, 7 nQ, Q Output Differential output pair. LVPECL interface levels.
8V
CC
Power Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
TABLE 3. FUNCTION TABLE
MR F_SEL Divide Value
1 X Reset: Q output low, nQ output high
00 ÷4
01 ÷5
FIGURE 1. TIMING DIAGRAM
CLK
MR
Q
REVISION A 2/12/15
87354 DATA SHEET
3 ÷4/÷5 DIFFERENTIAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 3.0V TO 3.465V, V
EE
= 0, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
CC
= 3.0V TO 3.465V, V
EE
= 0, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 3.0 3.3 3.465 V
I
EE
Power Supply Current 104 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
CC
= V
IN
= 3.465V 150 µA
nCLK V
CC
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current
CLK V
CC
= 3.465V, V
IN
= 0V -5 µA
nCLK V
CC
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
V
EE
+ 0.5 V
CC
- 0.85 V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current MR, F_SEL V
CC
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current MR, F_SEL V
CC
= 3.465V, V
IN
= 0V -5 µA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
CC
= 3.0V TO 3.465V, V
EE
= 0, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.

87354AMILF

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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