REVISION A 2/12/15
87354 DATA SHEET
7 ÷4/÷5 DIFFERENTIAL-TO-
3.3V LVPECL CLOCK GENERATOR
FIGURE 2C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet
the V
PP
and V
CMR
input requirements. Figures 2A to 2E show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 2A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confi rm the driver termination requirements. For
example in Figure 2A, the input termination applies for LVH-
STL drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
÷4/÷5 DIFFERENTIAL-TO-
3.3V LVPECL CLOCK GENERATOR
87354 DATA SHEET
8 REVISION A 2/12/15
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
REVISION A 2/12/15
87354 DATA SHEET
9 ÷4/÷5 DIFFERENTIAL-TO-
3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 87354.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 87354 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 104mA = 360mW
Power (outputs)
MAX
= 3.465mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 360mW + 30mW = 390mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming
a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.390W * 103.3°C/W = 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 8-PIN SOIC, FORCED CONVECTION
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

87354AMILF

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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