NB3N508SDTR2G

© Semiconductor Components Industries, LLC, 2006
October, 2006 Rev. 0
1 Publication Order Number:
NB3N508S/D
NB3N508S
3.3V, 216 MHz PureEdge
VCXO Clock Generator with
M−LVDS Output
Description
The NB3N508S is a high precision, low phase noise Voltage
Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that
generates 216 MHz MLVDS output from a 27 MHz crystal. The
±100 ppm output pullable range is obtained using the V
IN
pin of the
VCXO with usable range from 0 V to 3.3 V. The VCXO input pin V
IN
is a highimpedance input that can be driven directly from a pulse
width modulated RC integrator circuit.
The NB3N508S is designed primarily for data and clock recovery
applications within end products such as ADSL modems, settop box
receivers, and telecom systems. This device is housed in 5.0 mm x
4.4 mm narrow body TSSOP16 pin package.
Features
PureEdge Clock Family Provides Accuracy and Precision
Performs Precision Clock Multiplication from 27 MHz Crystal
Uses 27 MHz Fundamental Mode Crystal
External Loop Filter is Not Required
216 MHz MLVDS Output
VCXO with Pull Range $100 ppm
0 V to 3.3 V VCXO Tuning Voltage Range Capabilities
Phase Noise: Offset Noise Power
100 Hz 80 dBc
1 kHz 88 dBc
10 kHz 105 dBc
100 kHz 106 dBc
1 MHz 120 dBc
10 MHz 145 dBc
Operating Range 3.3 V $5%
These are PbFree Devices*
TSSOP16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
http://onsemi.com
1
16
NB3N
508S
ALYWG
G
1
16
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
NB3N508S
http://onsemi.com
2
Figure 1. NB3N508S Simplified Logic Diagram
BN
VCXO
Phase
Detector
Charge
Pump
VCO
MLVDS
Output
V
IN
27 MHz
Crystal
X2
X1
CLK
CLK
V
DD
GND
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
NB3N508S
http://onsemi.com
3
Figure 2. Pin Configuration (Top View)
CLK
X1
X2
NC
CLK
NB3N508S
V
DD
NC
NC
GND
V
DD
V
DD
GND
GND
GND
V
DD
V
IN
2
1
3
4
5
6
7
8
15
16
14
13
12
11
10
9
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 X1 Crystal Input Crystal input(IN). Connect to a 27 MHz crystal.
2, 3, 4, 10 V
DD
Power Supply Positive power supply voltage.
5 V
IN
Input Analog voltage input pin that controls output oscillation frequencies. V
IN
pin range is
from 0 V to 3.3 V. V
IN
voltage should not exceed V
DD
.
6, 7, 8, 12 GND Power Supply Ground 0 V. These pins provide GND return path for the devices.
9, 11, 15 NC No Connect.
13 CLK MLVDS Output
Inverted clock output. Typically loaded with 50 W receiver termination resistor across
diff. pair.
14 CLK MLVDS Output
Noninverted clock output. Typically loaded with 50 W receiver termination resistor
across diff. pair.
16 X2 Crystal Input Crystal input(OUT). Connect to a 27 MHz crystal.
Recommended Crystal Parameters
Crystal Fundamental ATCut Frequency 27 MHz
Load Capacitance 14 pF
Shunt Capacitance, C0 7 pF
Max Equivalent Series Resistance 35 W
Max Initial Accuracy at 25°C ±20 ppm
Temperature Stability ±30 ppm
Aging ±20 ppm
C0/C1 Ration 250 Max

NB3N508SDTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products VCXO CLK GEN MLVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet