NB3N508SDTR2G

NB3N508S
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4
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 4 kV
> 400 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP16 Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 6000 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
DD
Positive Power Supply GND = 0 V 4.6 V
V
I
Input Voltage (V
IN
) GND = 0 V GND v V
I
v V
DD
V
DD
V
I
OUT
MLVDS Output Current Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range 0 to +70 °C
T
STG
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance
(JunctiontoAmbient)
0 lfpm
500 lfpm
TSSOP–16
TSSOP–16
138
108
°C/W
°C/W
q
JA
Thermal Resistance (JunctiontoCase) (Note 2) TSSOP16 33 to 36 °C/W
T
SOL
Wave Solder PbFree 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board 2S2P (2 Signal, 2 Power).
Table 4. DC CHARACTERISTICS (V
DD
= 3.135 V to 3.465 V, GND = 0 V, T
A
= 0°C to +70°C)
Symbol Characteristic Min Typ Max Unit
I
DD
Power Supply Current (outputs loaded with R
L
= 50 W)
42 52 62 mA
V
IA
VCXO Control Voltage, V
IN
0 3.3 V
V
OD
Differential Output Voltage (Note 3) 480 565 650 mV
DV
OD
Change in Magnitude of V
OD
for Complementary Output States
(Notes 3, 6)
50 50 mV
V
OS
Offset Voltage (See Figure 4) 300 2100 mV
DV
OS
Change in Magnitude of V
OS
for Complementary Output States
(Note 6)
50 50 mV
V
OH
Output HIGH Voltage (Note 4) 1300 2425 mV
V
OL
Output LOW Voltage (Note 5) 25 700 mV
I
SC
Output Short Circuit Current CLK or CLK to GND 43 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. MLVDS outputs require 50 W receiver termination resistor between differential. pair. See Figure 3
4. V
OHmax
= V
OSmax
+ ½ V
ODmax
.
5. V
OLmax
= V
OSmin
½ V
ODmax
.
6. Parameters guaranteed by design but not tested in production.
NB3N508S
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Table 5. AC CHARACTERISTICS (V
DD
= 3.135 V to 3.465 V, GND = 0 V, T
A
= 0°C to +70°C, Note 7)
Symbol
Characteristic Min Typ Max Unit
f
CLKIN
Crystal Input Frequency 27 MHz
f
CLKOUT
Output Clock Frequency 216 MHz
F
NOISE
PhaseNoise Performance f
CLKOUT
= 216 MHz
@ 100 Hz Offset from Carrier
@ 1 kHz Offset from Carrier
@ 10 kHz Offset from Carrier
@ 100 kHz Offset from Carrier
@ 1 MHz Offset from Carrier
@ 10 MHz Offset from Carrier
80
88
105
106
120
145
dBc/Hz
Spurious Noise Components 60 dBc/Hz
F
P
Crystal Pullability 0 V v V
IN
v 3.3 V "100 ppm
t
DUTY_CYCLE
Output Clock Duty Cycle (Measured at Crosspoint) 45 50 55 %
t
R
Output Rise Time (CLK/CLK) (Note 8) 380 500 ps
t
F
Output Fall Time (CLK/CLK) (Note 8) 380 500 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. CLK/CLK loaded with 50 W receiver termination resistor between diff. pair.
8. Measured differentially (CLK CLK) at 10% to 90%; R
L
= 50 W.
Figure 3. Typical Phase Noise Plot (V
DD
= 3.3 V, V
IN
= 0 V; Room Temperature)
Phase Noise 10.00dB/Ref 20.00dBc/Hz
OFFSET FREQUENCY (Hz)
NOISE POWER (dBc)
NB3N508S
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250
200
150
100
50
0
50
100
150
200
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Maximum
Minimum
FREQUENCY ERROR (ppm)
Figure 4. VCXO Pulling Range
V
IN
, CONTROL VOLTAGE (V)
Figure 5. Output Clock Frequency vs. V
IN
and
Temperature
0 0.5 1.0 1.5 2.0 2.5 3.0 3.453.15 3.3
215.94
215.96
215.98
216
216.02
216.04
216.06
FREQUENCY (MHz)
V
IN
, CONTROL VOLTAGE (V)
70°
25°
0°
Figure 6. Typical Crystal Startup Time with
V
IN
= 0 V at Ambient Temperature (1.99 ms)
Figure 7. Typical Crystal Startup Time with
V
IN
= 3.3 V at Ambient Temperature (694 ms)
Figure 8. Typical Termination for Output Driver and Device Evaluation
Driver
Device
Receiver
Device
CLK D
CLK D
MLVDS
50 W
MLVDS
Z
o
= 50 W
Z
o
= 50 W
V
OL
CLK
V
OH
CLK
V
OS
V
OD
Figure 9. HLVDS Output

NB3N508SDTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products VCXO CLK GEN MLVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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