MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
Pin Description
PIN NAME FUNCTION
1, 12, 13 AGND Analog Ground
2 RCLK_R/F
Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe
ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of
RCLK.
3 REFCLK PLL Reference Clock. LVTTL/LVCMOS level input.
4, 11 AVCC Analog Power Supply. Bypass AVCC with a 0.1μF and a 0.001μF capacitor to AGND.
5 RI+ Serial Data Input. Noninverting BLVDS differential input.
6 RI- Serial Data Input. Inverting BLVDS differential input.
7 PWRDN
Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
8 REN
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance. LOCK remains active, indicating the status of the serial input.
9 RCLK Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
10 LOCK
Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
14, 20,
22
DGND Digital Ground
15–19,
24–28
ROUT9–
ROUT0
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low.
21, 23 DVCC Digital Power Supply. Bypass DVCC with a 0.1μF and a 0.001μF capacitor to DGND.
Figure 1. Worst-Case I
CC
Test Pattern
0 0
END
BIT
987654310
START
BIT
END
BIT
97654321 21
82
START
BIT
T
DD
RCLK_R/F = HIGH
START
BIT
RI
RCLK
ODD
ROUT
EVEN
ROUT
Test Circuits/Timing Diagrams
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