MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
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Detailed Description
The MAX9206/MAX9208 deserialize a BLVDS serializ-
er's output into 10-bit wide parallel LVCMOS/LVTTL
data and a parallel rate clock. The MAX9206/MAX9208
include a PLL that locks to the frequency and phase of
the serial input, and digital circuits that deserialize and
deframe the data. The MAX9206/MAX9208 have high-
input jitter tolerance while receiving data at speeds
from 160Mbps to 600Mbps. Combination with the
MAX9205/MAX9207 BLVDS serializers allows data
transmission across backplanes using PCB traces, or
across twin-ax or twisted-pair cables.
The MAX9206/MAX9208 deserializers provide a power-
saving, power-down mode when PWRDN is driven low.
The output enable, REN, allows the parallel data out-
puts (ROUT_) and recovered clock (RCLK) to be
enabled or disabled while maintaining lock to the serial
input. LOCK, along with RCLK, indicates when data is
valid at ROUT_. Parallel, deserialized data at ROUT_ is
strobed out on the selected strobe edge of RCLK. The
strobe edge of RCLK is programmable. The falling
edge is selected when RCLK_R/F is low and the rising
edge is selected when RCLK_R/F is high.
The interface may be point-to-point or a heavily loaded
bus. The characteristic impedance of the media and
connections can range from 100Ω for a point-to-point
interface to 54Ω for a heavily loaded bus. A double-ter-
minated point-to-point interface uses a 100Ω termina-
tion resistor at each end of the interface, resulting in a
total load of 50Ω. A heavily loaded bus with a termina-
tion as low as 54Ω at each end of the bus (resulting in a
total load of 27Ω) can be driven.
A high state bit and a low state bit, added by the
BLVDS serializer, frame each 10 bits of serial data and
create a guaranteed transition for clock recovery. The
high bit is prepended at the start and the low bit is
appended at the end of the 10-bit data. The rising edge
formed at the end/start bit boundary functions as an
embedded clock. Twelve serial bits (10 data + 2 frame)
are transmitted by the serializer and received by the
deserializer for each 10 bits of data transferred. The
MAX9206 accepts a 16MHz to 45MHz reference clock,
and receives serial data at 160Mbps (10 data bits x
16MHz) to 450Mbps (10 data bits x 45MHz). The
MAX9208 accepts a 40MHz to 60MHz reference clock,
and receives serial data at a rate of 400Mbps to
600Mbps.
Initialization
Initialize the MAX9206/MAX9208 before receiving data.
When power is applied, with REFCLK stable and
PWRDN high, RCLK and ROUT_ are held in high
impedance, LOCK goes high, and the on-chip PLL
locks to REFCLK in 2048 cycles. After locking to REF-
CLK, ROUT_ is active, RCLK tracks REFCLK, and
LOCK remains high. If transitions are detected at the
serial input, the PLL locks to the phase and frequency
of the serial input, finds the frame bits, and drives
LOCK low. If the serial input is sync patterns, LOCK
goes low in 42 or fewer cycles of RCLK. When LOCK
goes low, RCLK switches from tracking REFCLK to
tracking the serializer reference clock (TCLK).
Deserialized data at ROUT_ is valid on the second
selected strobe edge of RCLK after LOCK goes low.
Initialization restarts when power is cycled or on the ris-
ing edge of PWRDN.
Lock to Pseudorandom Data
The MAX9206/MAX9208 lock to pseudorandom serial
input data by deductively eliminating rising edges due
to data until the embedded end/start edge is found.
The end/start edge is identified unless the data con-
tains a permanent, consecutive, frame-to-frame rising
edge at the same bit position. Send sync patterns to
guarantee lock. A sync pattern is six consecutive ones
followed by six consecutive zeros, repeating every
RCLK period with only one rising edge (at the end/start
boundary). The MAX9205/MAX9207 serializers gener-
ate sync patterns when SYNC1 or SYNC2 is driven
high.
Since sending sync patterns to initialize a deserializer
disrupts data transfer to all deserializers receiving the
same serial input (Figure 11, for example), lock to
pseudorandom data is preferred in many applications.
Lock to pseudorandom data allows initialization of a
deserializer after hot insertion without disrupting data
communication on other links.
The MAX9206/MAX9208s’ deductive algorithm pro-
vides very fast pseudorandom data lock times. Table 1
compares typical lock times for pseudorandom and
sync pattern inputs.
Power-Down
Drive PWRDN low to enter the power-down mode. In
power-down, the PLL is stopped and the outputs
(ROUT_, RCLK, and LOCK) are put in high impedance,
disabling drive current and also reducing supply cur-
rent.
Output Enable
When the deserializer is initialized and REN is high,
ROUT_ is active, RCLK tracks the serializer reference
clock (TCLK), and LOCK is low. Driving REN low dis-
ables the ROUT_ and RCLK output drivers and does
not affect state machine timing. ROUT_ and RCLK go
