REV. 0–12–
AD74111
Table II. Serial Mode Selection
CRD:2 CRC:5, 4
CRD:3 DSP Word Operating
DM/MM Mode Width Mode Figure
0016 16-Bit Data Mode 15
0116 32-Bit Data Mode 19
1016 16-Bit Mixed Mode 13
1116 32-Bit Mixed Mode 17
00>16 16-Bit Data Mode 16
01>16 32-Bit Data Mode 20
10>16 16-Bit Mixed Mode 14
11>16 32-Bit Mixed Mode 18
DFS
(MM16)
DIN
1/
f
S
STATUS
(16 BITS)
DOUT
STATUS
(16 BITS)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
CONTROL
(16 BITS)
DAC
(16 BITS)
STATUS
(16 BITS)
ADC
(16 BITS)
CONTROL
(16 BITS)
DAC
(16 BITS)
STATUS
(16 BITS)
ADC
(16 BITS)
Figure 13. 16-Bit Mixed Mode, Word Length = 16 Bits
16 DCLKS
DFS
(MM16)
DIN
1/
f
S
DOUT
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
CONTROL
(16 BITS)
STATUS
(16 BITS)
DAC DATA
(24 BITS)
ADC DATA
(24 BITS)
CONTROL
(16 BITS)
STATUS
(16 BITS)
Figure 14. 16-Bit Mixed Mode, Word Length = 24 Bits
DFS
(MM16)
DIN
1/
f
S
STATUS
(16 BITS)
DOUT
STATUS
(16 BITS)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
DAC
(16 BITS)
ADC
(16 BITS)
DAC
(16 BITS)
ADC
(16 BITS)
Figure 15. 16-Bit Data Mode, Word Length = 16 Bits
there will be a fixed relationship between the instruction cycle
time of the DSP program and the AD74111, so a timer could be
used to accurately control the DAC updates. If a timer is not
available, the Multiframe-Sync (MFS) mode could be used to
generate a DFS pulse every 16 or 32 DCLKs, allowing the DSP
to accurately control the number of DCLKs between updates
using an autobuffering or DMA type technique. In all cases for
Slave mode operation, there should be 128 DCLKs (Normal
mode) or 256 DCLKs (Fast mode) between DAC updates. The
ADC operates in a similar manner; however, if the DSP does not
read an ADC result, this will appear only as a missed sample and
will not be audible. Slave mode is most suited to state-machine
type applications where the number of DCLKs and their
relationships to the other interface signals can be controlled.
