AD74111YRUZ-REEL Datasheet AD74111YRUZ-REEL7, AD74111YRUZ, AD74111YRUZ-REEL | P16-P18

REV. 0

AD74111

–15–

DAC DAC

ADC ADC

16 DCLKs

DFS

DIN

DOUT

Figure 24. Multiframe Sync 16-Bit Data Mode

Table III. Multiframe Sync Selection

CRD:9 CRD:3 CRC:2

MFS DM/MM DSP Mode Operating Mode Figure

10 0 16-Bit Data Mode 24

10 1 32-Bit Data Mode 22

11 0 16-Bit Mixed Mode 23

11 1 32-Bit Mixed Mode 21

Table IV. Control Register Map

Address (Binary) Name Description Type Width Reset Setting

0 0 0 0 CRA Control Register A R/W 10 00h

0 0 0 1 CRB Control Register B R/W 10 00h

0 0 1 0 CRC Control Register C R/W 10 00h

0 0 1 1 CRD Control Register D R/W 10 08h or 09h*

0 1 0 0 CRE Control Register E R/W 10 00h

0 1 0 1 CRF Control Register F R 10 00h

0 1 1 0 CRG Control Register G R/W 10 00h

*09h if DIN is low and 08h if DIN is high.

Table V. Control Word Descriptions

Bit Field Description

15 R/W When this bit is high, the contents of the data field will be written to the register specified by the Address

Field. When this bit is low, a read of the register specified by the Address Field will occur at the next

sample interval; the contents of the Data Field are ignored.

14–11 Register Address This 4-bit field is used to select one of the seven control registers of the AD74111.

10 Reserved This bit is reserved and should always be programmed with zero.

9–0 Data Field This 10-bit field holds the data that is to be written to or read from the register specified in the Address Field.

REV. 0–16–

AD74111

Table VII. Control Register B

Third MCLK Second MCLK First MCLK

R/W ADDRESS RES Reserved Divider Divider Divider

15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3, 2 1, 0

1 0001 0 0 00 = Divide by 1 00 = Divide by 1 00 = Divide by 1

01 = Divide by 2 01 = Divide by 2 01 = Divide by 2

10 = Divide by 4 10 = Divide by 3 10 = Divide by 3

11 = Divide by 1 11 = Divide by 1 11 = Divide by 1

Table VIII. Control Register C

DAC and ADC Low Group DAC ADC High-

R/W ADDRESS RES Reserved Word Width Delay De-emphasis Pass Filter

15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3 2, 1 0

1 0010 0 0 00 = 16 Bits 0 = Disabled 00 = None 0 = Disabled

01 = 20 Bits 1 = Enabled 01 = 44.1 kHz 1 = Enabled

10 = 24 Bits 10 = 32 kHz

11 = 24 Bits 11 = 48 kHz

Table IX. Control Register D

Master/

R/W ADDRESS RES Multiframe Sync Reserved DM/MM DSP Mode Fast DCLK Slave

15 14, 13, 12, 11 10 9 8, 7, 6, 5, 4 3 2 1 0

1 0011 0 0 = Normal Mode 0 0 = Data Mode 0 = 16 Bits 0 = 128 ⫻ f

0 = Slave

1 = MFS Mode 1 = Mixed Mode 1 = 32 Bits 1 = 256 ⫻ f

1 = Master

Table VI. Control Register A

ADC Input Reference

R/W ADDRESS RES Reserved Amplifier ADC DAC Reference Amplifier Reserved

15 14, 13, 12, 11 10 9, 8, 7 6 5 4 3 2 1, 0

1 0000 0 0 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0

1 = On 1 = On 1 = On 1 = On 1 = On

Function

REV. 0

AD74111

–17–

Table X. Control Register E

ADCL Peak ADC DAC

R/W ADDRESS RES Reserved Enable ADC Gain Mute Mute

15 14, 13, 12, 11 10 9, 8, 7, 6 5 4, 3, 2 1 0

1 0100 0 0 0 = Disabled 000 = 0 dB 0 = Normal 0 = Normal

1 = Peak Enable 001 = 3 dB 1 = Mute 1 = Mute

010 = 6 dB

011 = 9 dB

1XX = 12 dB

Function

Table XI. Control Register F

R/W ADDRESS RES Reserved ADC Input Peak Level

15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4, 3, 2, 1, 0

000000 = 0 dBFS

000001 = –1 dBFS

0 0101 0 0 000010 = –2 dBFS

111110 = –62 dBFS

111111 = –63 dBFS

Function

Table XII. Control Register G

R/W ADDRESS RES DAC Volume

15 14, 13, 12, 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

0000000000 = 0 dBFS

0000000001 = (1023/1024) dBFS

1 0110 0 0000000010 = (1022/1024) dBFS

1111111110 = (2/1024) dBFS

1111111111 = Mute

Function

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD74111YRUZ-REEL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Interface - CODECs 2.5V 24B Mono CODEC

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AD74111YRUZ-REEL

AD74111YRUZ-REEL

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