74AUP1G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 28 June 2012 9 of 21
NXP Semiconductors
74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PZL
and t
PLZ
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
T
amb
= 25 C
C
PD
power dissipation capacitance f = 1 MHz; V
I
= GND to V
CC
[3]
V
CC
= 0.8 V - 2.7 - pF
V
CC
= 1.1 V to 1.3 V - 2.9 - pF
V
CC
= 1.4 V to 1.6 V - 3.0 - pF
V
CC
= 1.65 V to 1.95 V - 3.1 - pF
V
CC
= 2.3 V to 2.7 V - 3.6 - pF
V
CC
= 3.0 V to 3.6 V - 4.2 - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol Parameter Conditions Min Typ
[1]
Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
C
L
= 5 pF
t
pd
propagation delay A or B to Y; see Figure 8
[1]
V
CC
= 1.1 V to 1.3 V 2.1 14.3 2.1 15.8 ns
V
CC
= 1.4 V to 1.6 V 1.6 8.8 1.6 9.7 ns
V
CC
= 1.65 V to 1.95 V 1.4 6.9 1.4 7.6 ns
V
CC
= 2.3 V to 2.7 V 1.1 5.3 1.1 5.9 ns
V
CC
= 3.0 V to 3.6 V 0.9 4.7 0.9 5.2 ns
C
L
= 10 pF
t
pd
propagation delay A or B to Y; see Figure 8
[1]
V
CC
= 1.1 V to 1.3 V 2.4 16.2 2.4 17.9 ns
V
CC
= 1.4 V to 1.6 V 1.9 10.0 1.9 11.0 ns
V
CC
= 1.65 V to 1.95 V 1.7 8.0 1.7 8.8 ns
V
CC
= 2.3 V to 2.7 V 1.4 6.2 1.4 6.9 ns
V
CC
= 3.0 V to 3.6 V 1.3 5.6 1.3 6.2 ns
