8
Table 6. Switching Speci cations
Over recommended operating conditions T
A
= -40° C to 105° C, V
CC
= +4.5 V to 30 V, I
F(ON)
= 4 mA to 7 mA, V
F(OFF)
= 0 V
to 0.8 V, unless otherwise speci ed. All typicals at T
A
= 25° C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time
to Logic Low Output Level
t
PHL
75 120 ns C
L
= 100pF, V
F
= 0 V I
F(OFF)
= 4 mA 5, 6, 8 6
120 Loaded as per Fig. 5
Propagation Delay Time
to Logic High Output Level
t
PLH
75 120 ns C
L
= 100 pF, I
F(OFF)
= 4 mA V
F
= 0 V 5, 6, 8 6
120 Loaded as per Fig. 5
Pulse Width Distortion |t
PHL
- t
PLH
|
= PWD
50 ns C
L
= 100 pF 5, 6, 8 9
50 Loaded as per Fig. 5
Propagation Delay
Di erence Between
Any 2 Parts
PDD –100 100 ns C
L
= 100 pF 5, 6, 8 10
–100 100 Loaded as per Fig. 5
Output Rise Time (10-90%) t
r
6ns 5
Output Fall Time (90-10%) t
f
6ns 5
Logic High Common Mode
Transient Immunity
|CM
H
| 30 kV/s|V
CM
| = 1000 V, V
F
= 0 V,
V
CC
= 5 V, T
A
= 25°C
97
Logic Low Common Mode
Transient Immunity
|CM
L
| 30 kV/s|V
CM
| = 1000 V, I
F
= 4.0 mA,
V
CC
= 5 V, T
A
= 25°C
97
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage*
V
ISO
3750 (ACPL-M483
and P483)
5000 (ACPL-W483)
V
rms
RH < 50%, t = 1 min.
T
A
= 25°C
5, 8
Input-Output Resistance R
I-O
10
12
Ohm V
I-O
= 500 V
dc
5
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz, V
I-O
= 0 V
dc
5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).
Inverted UVLO
Figures 10a and b show typical output waveforms during Power-up and Power-down processes.
Notes:
1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5mW/°C (ACPL-P483/W483) and linearly above
85°C free-air temperature at a rate of 0.75 mW/°C (ACPL-M483).
2. Detector requires a Vcc of 4.5 V or higher for stable operation as output might be unstable if Vcc is lower than 4.5 V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 500 s.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The t
PLH
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The t
PHL
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse. Peaking capacitor, C1 = 120 pF must be connected as shown in Figure 5.
7. CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V
O
> 2.0 V.
CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V
O
< 0.8 V. Note:
Equal value split resistors (Rin/2) must be used at both ends of the LED.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 V
RMS
for one second (leakage detection
current limit, I
I-O
< = 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN
60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is de ned as |t
PHL
- t
PLH
| for any given device.
10. The di erence of tPLH and tPHL between any two devices under the same test condition.
11. Use of a 0.1 F bypass capacitor connected between pins Vcc and Ground is recommended.
