10
The 33% maximum duty cycle of the converter guarantees
discontinuous inductor current and unconditional stability
over all operating conditions.
The boost converter with the limited duty cycle and
discontinuous inductor current can deliver to the load a
limited amount of power before the output voltage starts to
drop. When the duty cycle has reached DMAX, the control
loop is operating open circuit and the output voltage varies
with the output load resistance, Ro, as given by:
Where Vin is the 5V Main voltage, Dmax = 0.33, L is the
value of the boost inductor, L3, and F = 100kHz. This
provides automatic output current limiting. When the
maximum duty cycle has been reached and for a given
inductor, a further reduction in Ro by one-half will pull the
output voltage down to 0.707 of nominal and cause an
undervoltage condition.
The 12V converter starts to operate at the same time as the
5V Main converter. The rising voltage on the 5V Main output
and the 33% duty cycle limit provides a similar soft-start, as
the 5V Main, for the 12V output.
3V ALWAYS, 5V ALWAYS Linear Regulators
The 3.3V ALWAYS and 5V ALWAYS outputs are derived
from the battery voltage and are the first voltages available
in the notebook when power on is initiated. The 5V ALWAYS
output is generated directly from the battery voltage by a
linear regulator. It is used to power the system micro-
controller and to internally power the chip and the gate
drivers. The 3.3V ALWAYS output is generated from the 5V
ALWAYS output and may be used to power the keyboard
controller or other peripherals. The combined current
capability of these outputs is 50mA. When the 5V Main
output is greater than it’s undervoltage level, it is switched to
the 5V ALWAYS output via an internal 1.3
MOSFET
switch. Simultaneously, the 5V ALWAYS linear regulator is
disabled to prevent excessive power dissipation.
The rise time of the 5V ALWAYS is determined by the value
of the output capacitance on the 5V and 3.3V ALWAYS
outputs. The internal regulator is current limited to about
180mA, so the startup time is approximately:
Where C
OUT
is the sum of the capacitances on the 5V and
3.3V ALWAYS outputs.
Power Good Status
The IPM6220A monitors all the output voltages except for
the 3.3V ALWAYS. A single power-good signal, PGOOD, is
issued when soft-start is completed and all monitored
outputs are within 10% of their respective set points. After
the soft-start sequence is completed, undervoltage
protection latches the chip off when any of the monitored
outputs drop below 75% of its set point.
A ‘soft-crowbar’ function is implemented for an overvoltage
on the 3.3V Main or 5V Main outputs. If the output voltage
goes above 115% of their nominal output level, the upper
MOSFET is turned off and the lower MOSFET is turned on.
This ‘soft-crowbar’ condition will be maintained until the
output voltage returns to the regulation window and then
normal operation will continue.
This ‘soft-crowbarand monitoring of the output, prevents the
output voltage from ringing negative as the inductor current
flows in the ‘reverse’ direction through the lower MOSFET
and output capacitors.
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts all the outputs down when the die temperature
exceeds 150°C. Normal operation is automatically restored
when the die temperature cools to 125°C.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements
including ripple voltage and load transients.
3.3V Main and 5V Main PWM Output Capacitors
Selection of the output capacitors is also dependent on the
output inductor so some inductor analysis is required to
select the output capacitors.
-
EA3
REF
+
Q
Q
R
S
PWM
LATCH 3
VSEN3
+
-
CLK
DIVIDER
3:1
RAMP
GENERATOR
CLK/3
CLK/3
GATE3
RAMP
t
t
t
t
CLK
CLK/3
RAMP
VEA3
GATE3
PWM
COMPARATOR
FIGURE 8. 12V BOOST OPERATION
Vo Vin Dmax
Ro
2LxF
-------------------


=
tC
OUT
5V
180mA
-------------------
=
IPM6220A
11
One of the parameters limiting the converter’s response to a
load transient is the time required for the inductor current to
slew to its new level. Given a sufficiently fast control loop
design, the IPM6220A will provide either 0% or 94% duty
cycle in response to a load transient. The response time is
the time interval required to slew the inductor current from an
initial current value to the load current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required. Also, if the load transient rise
time is slower than the inductor response time, as in a hard
drive or CD drive, this reduces the requirement on the output
capacitor.
The maximum capacitor value required to provide the full,
rising step, transient load current during the response time of
the inductor is:
Where: C
OUT
is the output capacitor(s) required, L
O
is the
output inductor, I
TRAN
is the transient load current step, V
IN
is the input voltage, V
OUT
is output voltage, and V
OUT
is
the drop in output voltage allowed during the load transient.
High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Equivalent Series Resistance) and
voltage rating requirements as well as actual capacitance
requirements. The output voltage ripple is due to the inductor
ripple current and the ESR of the output capacitors as
defined by:
where, I
L
is calculated in the Inductor Selection section.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load
circuitry for specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications, at 300kHz, for the bulk
capacitors. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
The stability requirement on the selection of the output
capacitor is that the ‘ESR zero’, f
Z
, be between 1.2kHz and
30kHz. This range is set by an internal, single compensation
zero at 6kHz. The ESR zero can be a factor of five on either
side of the internal zero and still contribute to increased
phase margin of the control loop. Therefore:
In conclusion, the output capacitors must meet three criteria: By
varying the values of the soft-start capacitors, it is possible to
provide sequencing of the main outputs at start-up.
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load
transient
2. The ESR must be sufficiently low to meet the desired
output voltage ripple due to the output inductor current,
and
3. The ESR zero should be placed, in a rather large range,
to provide additional phase margin.
3.3V ALWAYS and 5V ALWAYS Output Capacitors
The output capacitors for the linear regulators insure stability
and provide dynamic load current. The 3.3V ALWAYS and
the 5V ALWAYS linear regulators should have, as a
minimum, 10F capacitors on their outputs.
3.3V Main and 5V Main PWM Output Inductor
Selection
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and output capacitor(s) ESR. The ripple voltage
expression is given in the capacitor selection section and the
ripple current is approximated by the following equation:
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and 1.5 times is a conservative
guideline.
The AC RMS input current varies with load as shown in
Figure 9. Depending on the specifics of the input power and
its impedance, most (or all) of this current is supplied by the
input capacitor(s). Figure 9 also shows the advantage of
having the PWM converters operating out of phase. If the
converters were operating in-phase, the combined RMS
current would be the algebraic sum, which is a much larger
value as shown. The combined out-of-phase current is the
square root of the sum of the square of the individual
reflected currents and is significantly less than the combined
in-phase current.
C
OUT
L
O
I
TRAN
V
IN
V
OUT
2
----------------------------------------------
I
TRAN
DV
OUT
--------------------
=
V
RIPPLE
I
L
ESR=
C
OUT
1
2 ESR f
Z
-------------------------------------------
=
I
L
V
IN
V
OUT
F
S
L
--------------------------------
V
OUT
V
IN
----------------
=
IPM6220A
OS-CON® is a registered trademark of Sanyo Electric Company, Ltd. (Japan)
12
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CON® series offer low ESR and good
temperature performance.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the
capacitor surge current rating. These capacitors must be
capable of handling the surge-current at power-up. The TPS
series available from AVX is surge current tested.
+12V Boost Converter Inductor Selection
The inductor value is chosen to provide the required output
power to the load.
where, Vinmin is the minimum input voltage, 4.9V; Dmax =
1/3, the maximum duty cycle; Ro is the minimum load
resistance; Vo is the nominal output voltage and F is the
switching frequency, 100kHz.
+12V Boost Converter Output Capacitor Selection
The total capacitance on the 12V output should be chosen
appropriately, so that the output voltage will be higher than
the undervoltage limit (9V) when the 5V Main soft-start time
has elapsed. This will avoid triggering of the 12V
undervoltage protection.
The maximum value of the boost capacitor, Comax that will
charge to 9V in the soft-start time, Tss, is shown below,
where L is the value of the boost inductor.
The output capacitor ESR and the boost inductor ripple
current determines the output voltage ripple. The ripple
voltage is given by:
and the maximum ripple current, I
L,
is given by:
where L is the boost inductor calculated above, 5V is the
boost input voltage and 3.3 is the maximum on time for the
boost MOSFET.
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon r
DS(ON)
, gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the IPM6220A and do not heat the MOSFETs.
However, a large gate-charge increases the switching time,
t
SW
, which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. The voltage spikes can
degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turn-off transition of
one of the upper PWM MOSFETs. Prior to turn-off, the upper
MOSFET is carrying the full load current. During the turn-off,
current stops flowing in the upper MOSFET and is picked up
by the lower MOSFET. Any inductance in the switched current
path generates a voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
Lmax
Vinmin
2
Dmax
2
Ro
2Vo
2
F
----------------------------------------------------------------
=
Comax
Tss
L
----------
0.115F=
V
RIPPLE
I
L
ESR=
I
L
5V
L
-------
3.3=
P
UPPER
I
O
2
r
DS ON
V
OUT
V
IN
------------------------------------------------------------
I
O
V
IN
t
SW
F
S
2
----------------------------------------------------
+=
P
LOWER
I
O
2
r
DS ON
V
IN
V
OUT

V
IN
---------------------------------------------------------------------------------
=
IPM6220A

IPM6220ACAZA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers W/ANEAL 30V CS80 FSC PROCESS W/IMPROVED
Lifecycle:
New from this manufacturer.
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