IPM6220ACAZA-T Datasheet IPM6220ACAZA-T, IPM6220ACAZ, IPM6220ACAZ-T | P7-P9

converters for 5V Main and 3.3V Main buses, two linear

regulators for 3.3V ALWAYS and 5V ALWAYS, and a 12V

boost converter.

The two synchronous converters operate out of phase to

substantially reduce the input-current ripple, minimizing input

filter requirements, minimizing battery heating and

prolonging battery life.

The 12V boost controller uses a 100kHz clock derived from

the main clock. This controller uses leading edge modulation

with the maximum duty cycle limited to 33%.

The chip has three input control lines SDWN1

, SDWN2 and

SDWNALL

. These are provided for Advanced Configuration

and Power Interface (ACPI) compatibility. They turn on and

off all outputs, as well as provide independent control of the

3.3V Main and +5V Main outputs.

To maximize efficiency for the 5V Main and 3.3V Main outputs,

the current-sense technique is based on the lower MOSFET

DS(ON).

Light-load efficiency is further enhanced by a

hysteretic mode of operation which is automatically engaged at

light loads when the inductor current becomes discontinuous.

3.3V Main and 5V Main Architecture

These main outputs are generated from the unregulated

battery input by two independent synchronous buck

converters. The IC integrates all the components required

for output voltage setpoint and feedback compensation,

significantly reducing the number of external components,

saving board space and parts cost.

The buck PWM controllers employ a 300kHz fixed frequency

current-mode control scheme with input voltage feed-

forward ramp programming for better rejection of input

voltage variations.

Figure 4 shows the out-of-phase operation for the 3.3V Main

and 5V Main outputs. The phase node is the junction of the

upper MOSFET, lower MOSFET and the output inductor.

The phase node is high when the upper MOSFET is

conducting and the inductor current rises accordingly. When

the phase node is low, the lower MOSFET is conducting and

the inductor current is ramping down as shown.

Current Sensing and Current Limit Protection

Both PWM converters use the lower MOSFET on-state

resistance, r

DS(ON)

, as the current-sensing element. This

technique eliminates the need for a current sense resistor

and the associated power losses. If more accurate current

protection is desired, current sense resistors may be used in

series with the lower MOSFETs’ source.

To set the current limit, place a resistor, RSNS, between the

ISEN inputs and the drain of the lower MOSFET (or optional

current sense resistor). The required value of the RSNS

resistor is determined from the following equation:

where IOCDC is the desired DC overcurrent limit; RCS is

either the r

DS(ON)

of the lower MOSFET, or the value of the

optional current-sense resistor, Vo is the output voltage and L

is the output inductor. Also, the value of RCS should be

specified for the expected maximum operating

temperature.

The sensed voltage, and the resulting current out of the

ISEN pin through RSNS, is used for current feedback and

current limit protection. This is compared with an internal

current limit threshold. When a sampled value of the output

current is determined to be above the current limit

threshold, the PWM drive is terminated and a counter is

initiated. This limits the inductor current build-up and

essentially switches the converter into current-limit mode. If

an overcurrent is detected between 26s to 53s later, an

overcurrent shutdown is initiated. If during the 26s to 53s

period, an overcurrent is not detected, the counter is reset

and sampling continues as normal.

This current limit scheme has proven to be very robust in

applications like portable computers where fast inductor

current build-up is common due to a large difference

between input and output voltages and a low value of the

inductor.

Light-Load (Hysteretic) Operation

In the light-load (hysteretic) mode the output voltage is

regulated by the hysteretic comparator which regulates the

output voltage by maintaining the output voltage ripple as

shown in Figure 5. In Hysteretic mode, the inductor current

flows only when the output voltage reaches the lower limit of

the hysteretic comparator and turns off at the upper limit.

Hysteretic mode saves converter energy at light loads by

supplying energy only at the time when the output voltage

requires it. This mode conserves energy by reducing the

power dissipation associated with continuous switching.

RSNS

Rcs

135A

------------------

Iocdc

L2300kHz

-----------------------------------------





100–=

0 A, V

5V PHASE (10V/DIV.)

1s/DIV.

L3.3V

(2A/DIV.)

L5V

(2A/DIV.)

= 10.8V

3.3V PHASE (10V/DIV.)

FIGURE 4. OUT OF PHASE OPERATION

IPM6220A

During the time between inductor current pulses, both the

upper and lower MOSFETs are turned off. This is referred to

as ‘diode emulation mode’ because the lower MOSFET

performs the function of a diode. This diode emulation mode

prevents the output capacitor from discharging through the

lower MOSFET when the upper MOSFET is not conducting.

The gate drive is synchronized to the main clock, so the out-

of-phase timing is maintained in hysteretic mode. Such a

scheme insures a seamless transition between the

operational modes.

Operation-Mode Control

The mode-control circuit changes the converter’s mode of

operation based on the voltage polarity of the phase node

when the lower MOSFET is conducting and just before the

upper MOSFET turns on. For continuous inductor current,

the phase node is negative when the lower MOSFET is

conducting and the converters operate in fixed-frequency

PWM mode as shown in Figure 6. When the load current

decreases to the point where the inductor current flows

through the lower MOSFET in the ‘reverse’ direction, the

phase node becomes positive, and the mode is changed to

hysteretic.

A phase comparator handles the timing of the phase node

voltage sensing. A low level on the phase comparator output

indicates a negative phase voltage during the conduction

time of the lower MOSFET. A high level on the phase

comparator output indicates a positive phase voltage.

When the phase node is positive (phase comparator high),

at the end of the lower MOSFET conduction time, for eight

consecutive clock cycles, the mode is changed to hysteretic

as shown in Figure 6. The dashed lines indicate when the

phase node goes positive and the phase comparator output

goes high. The solid vertical lines at 1,2,...8 indicate the

sampling time, of the phase comparator, to determine the

polarity (sign) of the phase node. At the transition between

PWM and hysteretic mode, both the upper and lower

MOSFETs are turned off. The phase node will ‘ring’ based

on the output inductor and the parasitic capacitance on the

phase node and settle out at the value of the output voltage.

The mode change from hysteretic to PWM can be caused by

one of two events. One event is the same mechanism that

causes a PWM to hysteretic transition. But instead of looking

for eight consecutive positive occurrences on the phase

node, it is looking for eight consecutive negative

occurrences on the phase node. The operation mode will be

changed from hysteretic to PWM when these eight

consecutive pulses occur. This transition technique prevents

jitter of the operation mode at load levels close to boundary.

The other mechanism for changing from hysteretic to PWM

is due to a sudden increase in the output current. This step

load causes an instantaneous decrease in the output voltage

due to the voltage drop on the output capacitor ESR. If the

decrease causes the output voltage to drop below the

hysteretic regulation level, the mode is changed to PWM on

the next clock cycle. This insures the full power required by

the increase in output current.

Gate Control Logic

The gate control logic translates generated PWM control

signals into the MOSFET gate drive signals providing

necessary amplification, level shifting and shoot-through

protection. Also, it has functions that help optimize the IC

performance over a wide range of operational conditions.

Since MOSFET switching time can vary dramatically from

type to type and with the input voltage, the gate control logic

provides adaptive dead time by monitoring the gate-to-

source voltages of both upper and lower MOSFETs. The

lower MOSFET is not turned on until the gate-to-source

voltage of the upper MOSFET has decreased to less than

approximately 1 volt. Similarly, the upper MOSFET is not

turned on until the gate-to-source voltage of the lower

MOSFET has decreased to less than approximately 1 volt.

This allows a wide variety of upper and lower MOSFETs to

be used without a concern for simultaneous conduction, or

shoot-through.

PWM

HYSTERETIC

1 2 3 4 5 6 7 8

VOUT

PHASE

COMP

OPERATION

MODE

FIGURE 5. REGULATION IN HYSTERETIC MODE

PWM

HYSTERETIC

1 2 3 4

5 6

7 8

PHASE

COMP

OPERATION

MODE

PHASE

NODE

FIGURE 6. MODE CONTROL WAVEFORMS

IPM6220A

3.3V Main and 5V Main Soft Start, Sequencing and

Stand-by

See Table 1 for the output voltage control algorithm. The 5V

Main and 3.3V Main converters are enabled if SDWN1

and

SDWN2

are high and SDWNALL is also high. The stand-by

mode is defined as a condition when SDWN1

and SDWN2 are

low and the PWM converters are disabled but SDWNALL

high (3.3V ALWAYS and 5V ALWAYS outputs are enabled). In

this power saving mode, only the low power micro-controller

and keyboard may be powered.

Soft start of the 3.3V Main and 5V Main converters is

accomplished by means of capacitors connected from pins

SDWN1

and SDWN2 to ground. In conjunction with 5A

internal current sources, they provide a controlled rise of the

3.3V Main and 5V Main output voltages. The value of the

soft-start capacitors can be calculated from the following

expression.

Where Tss

is the desired soft-start time.

By varying the values of the soft-start capacitors, it is possible

to provide sequencing of the main outputs at startup.

Figure 7 shows the soft-start initiated by the SDWNALL

being pulled high with the Vbatt input at 10.8V and the

resulting 3.3V Main and 5V Main outputs.

While the SDWNALL

pin is held low, prior to T0, all outputs

are off. Pulling SDWNALL

high enables the 3.3V ALWAYS

and 5V ALWAYS outputs. With the 3.3V Main and 5V Main

outputs enabled, at T1, the internal 5A current sources start

charging the soft start capacitors on the SDWN1

and

SDWN2

pins. At T2 the outputs begin to rise and because

they both have the same value of soft-start capacitors,

0.022F, they both reach regulation at the same time, T3.

The soft-start capacitors continue to charge and are

completely charged at T4.

12V Converter Architecture

The 12V boost converter generates its output voltage from

the 5V Main output. An external MOSFET, inductor, diode

and capacitor are required to complete the circuit. The

output signal is fed back to the controller via an external

resistive divider. The boost controller can be disabled by

connecting the VSEN3 pin to 5V ALWAYS.

The control circuit for the 12V converter consists of a 3:1

frequency divider which drives a ramp generator and resets

a PWM latch as shown in Figure 8. The width of the CLK/3

pulses is equal to the period of the main clock, limiting the

duty cycle to 33%. The output of a non-inverting error

amplifier is compared with the rising ramp voltage. When the

ramp voltage becomes higher than the error signal, the

PWM comparator sets the latch and the output of the gate

driver is pulled high providing leading edge, voltage mode

PWM. The falling edge of the CLK/3 pulses resets the latch

and pulls the output of the gate driver low.

TABLE 1. OUTPUT VOLTAGE CONTROL

SDWNALL SDWN1 SDWN2

3V AND 5V

ALWAYS 5V MAIN 3V MAIN

0XXOFFOFFOFF

100ONOFFOFF

110ONONOFF

101ONOFFON

111ONONON

Css

5ATss

3.5V

----------------------------

SDWN2, 2V/DIV.

3.3V

OUT

, 2V/DIV.

OUT

, 2V/DIV.

4ms/DIV.

SDWN1, 2V/DIV.

T0 T1 T2 T3 T4

SDWNALL,10V/DIV.

= 10.8V

FIGURE 7. SOFT-START ON 3.3V AND 5V OUTPUTS

IPM6220A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

IPM6220ACAZA-T

Mfr. #:

Buy IPM6220ACAZA-T

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers W/ANEAL 30V CS80 FSC PROCESS W/IMPROVED

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

IPM6220ACAZA-T

IPM6220ACAZA-T

Products related to this Datasheet