1
PS8656A 05/27/03
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
V
DDQ
Q3
Q4
Q5
GND
V
DDQ
Q6
Q7
V
DDQ
GND
Q8
Q9
V
DDQ
GND
Q10
Q11
Q12
V
DDQ
GND
Q13
Q14
D1
D2
GND
V
DD
D3
D4
D5
D6
D7
CLK
CLK
V
DD
GND
V
REF
RESET
D8
D9
D10
D11
D12
V
DD
GND
D13
D14
Product Description
Pericom Semiconductor’s PI74SSTVF16857 series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857 universal bus driver is designed
for 2.5V to 2.6V V
DD
operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as V
REF
may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTVF16857 is characterized for operation from
0° to 70°C.
Product Features
• PI74 SSTVF16857 is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Pb-free available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
Product Pin Configuration
Product Pin Description
48-Pin
A, K
stupnIstuptuO
TESERKLCKLCDQ
LXXXL
H
↑↓
HH
Η↑↓
LL
HHroLHroLXoQ
)2(
Truth Table
(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH-to-LOW
X = Irrelevant
PI74SSTVF16857
14-Bit Registered Buffer
2. Output level before the
indicated steady state
input conditions were
established.
TO 13 OTHER CHANNELS
RESET
CLK
38
39
V
REF
D1
48
35
D
R
CLK
Q1
1
CLK
V
34
Pin Name Description
RESET Reset (Active Low)
CLK Clock Input
CLK Clock Input
D Data Input
Q Data Output
GND Ground
V
DD
Core Supply Voltage
V
DDQ
Output Supply Voltage
V
REF
Input Reference Voltage
