FSDM0565R
13
output voltage may exceed the rated voltage before the over
load protection is activated, resulting in the breakdown of the
devices in the secondary side. In order to prevent this
situation, an over voltage protection (OVP) circuit is
employed. In general, Vcc is proportional to the output
voltage and the FPS
TM
uses Vcc instead of directly
monitoring the output voltage. If V
CC
exceeds 19V, an OVP
circuit is activated resulting in the termination of the
switching operation. In order to avoid undesired activation of
OVP during normal operation, Vcc should be designed to be
below 19V.
3.4 Thermal Shutdown (TSD) : The Sense FET and the
control IC are built in one package. This makes it easy for
the control IC to detect the heat generation from the Sense
FET. When the temperature exceeds approximately 150°C,
the thermal shutdown is activated.
4. Soft Start : The FPS
TM
has an internal soft start circuit
that increases PWM comparator inverting input voltage
together with the Sense FET current slowly after it starts up.
The typical soft start time is 10msec, The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention of
smoothly establishing the required output voltage. It also
helps to prevent transformer saturation and reduce the stress
on the secondary diode during startup.
5. Burst operation : In order to minimize power dissipation
in standby mode, the FPS
TM
enters burst mode operation.
As the load decreases, the feedback voltage decreases. As
shown in figure 9, the device automatically enters burst
mode when the feedback voltage drops below
V
BURL
(500mV). At this point switching stops and the
output voltages start to drop at a rate dependent on standby
current load. This causes the feedback voltage to rise. Once
it passes V
BURH
(700mV) switching resumes. The feedback
voltage then falls and the process repeats. Burst mode
operation alternately enables and disables switching of the
power Sense FET thereby reducing switching loss in
Standby mode.
Figure 9. Waveforms of burst operation
V
FB
Vds
0.5V
0.7V
Ids
Vo
Vo
set
time
Switching
disabled
T1
T2 T3
Switching
disabled
T4
