MAX7490/MAX7491
Dual Universal Switched-Capacitor Filters
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FILTER
Center Frequency Range f
O
Mode 1
0.001 to
40
kHz
Clock-to-Center Frequency
Accuracy
f
CLK
/f
O
Mode 1, R1 = R3 = 50kΩ , R2 = 10kΩ,
Q = 5, deviation from 100:1
±0.2 ±0.7 %
Q Accuracy
Mode 1, R1 = R3 = 50kΩ, R2 = 10kΩ,
Q = 5
±0.2 ±2%
f
O
Temperature Coefficient ±1 ppm/°C
Q Temperature Coefficient ±5 ppm/°C
DC Lowpass Gain Accuracy Mode 1, R1 = R2 = 10kΩ±0.1 ±0.5 %
V
OS1
DC offset of input inverter ±3 ±12.5
V
OS2
DC offset of 1st integrator ±4 ±15
DC Offset Voltage
(Figure 8)
V
OS3
DC offset of 2nd integrator ±4 ±25
mV
Crosstalk (Note 2) f
IN
= 10kHz -60 dB
Input: COM externally driven
V
DD
/2
- 0.1
V
DD
/2
V
DD
/2
+ 0.1
COM Voltage Range V
COM
Output: COM internally driven
V
DD
/2
- 0.1
V
DD
/2
V
DD
/2
+ 0.1
V
Input Resistance at COM R
COM
60 80 120 kΩ
Clock Feedthrough Up to 5th harmonic of f
CLK
200 μV
RMS
Noise (Note 3)
Mode 1, R1= R2 = R3 = 10kΩ,
LP output, Q = 1
60 μV
RMS
Output Voltage Swing 0.2 V
D D
- 0.2 V
Input Leakage Current at COM SHDN = GND, V
COM
= 0 to V
DD
±0.1 ±10 μA
CLOCK
Maximum Clock Frequency f
CLK
4 MHz
EXTCLK = GND, C
OSC
= 1000pF 95 135 175 kHz
Internal Oscillator Frequency
(Note 4)
f
OSC
EXTCLK = GND, C
OSC
= 100pF 1.35 MHz
Clock Input High V
DD
- 0.5 V
Clock Input Low 0.5 V
Clock Duty Cycle 50 ±5%
SHDN AND EXTCLK
Input High V
IH
V
DD
- 0.5 V
Input Low V
IL
0.5 V
Input Leakage Current V
INPUT
= 0 to V
DD
±0.4 ±10 μA
ELECTRICAL CHARACTERISTICS—MAX7491
(V
DD
= V
EXTCLK
= +3V; f
CLK
= 625kHz; 10kΩ || 50pF load to V
DD
/2 at LP_, BP_, and N_/HP_; V
SHDN
= V
DD
; 0.1µF from COM to
GND; 50% duty-cycle clock input; COM = V
DD
/2; T
A
= T
MIN
to T
MAX
. Typical values are at T
A
= +25°C, unless otherwise noted.)
(Note 1)