6
LTC1530
1530fa
COMP to compensate the feedback loop for optimum
transient response. To shut down the LTC1530, pull this
pin below 0.1V with an open-collector or open-drain
transistor. Supply current is typically reduced to 45µA in
shutdown. An internal 4µA pullup ensures start-up.
I
MAX
(Pin 5): Current Limit Threshold. Current limit is set
by the voltage drop across an external resistor connected
between the drain of Q1 and I
MAX
. This voltage is com-
pared with the voltage across the R
DS(ON)
of the high side
MOSFET. The LTC1530 contains a 200µA internal pull-
down at I
MAX
to set current limit. This 200µA current
source has a positive temperature coefficient to provide
first order correction for the temperature coefficient of the
external N-channel MOSFET’s R
DS(ON)
.
I
FB
(Pin 6): Current Limit Sense Pin. Connect I
FB
to the
switching node between Q1’s source and Q2’s drain. If I
FB
drops below I
MAX
with G1 on, the LTC1530 enters current
limit. Under this condition, the internal soft-start capacitor
is discharged and COMP is pulled low slowly. Duty cycle
is reduced and output power is limited. The current limit
circuitry is only activated if PV
CC
≥ 8V. This action eases
start-up considerations as PV
CC
is ramping up because
the MOSFET’s R
DS(ON)
can be significantly higher than
what is measured under normal operating conditions. The
current limit circuit is disabled by floating I
MAX
and short-
ing I
FB
to PV
CC
.
G2 (Pin 7): Gate Drive for the Low Side N-Channel MOSFET,
Q2. This output swings from PV
CC
to GND. It is always low
if G1 is high or if the output is disabled. To prevent
undershoot during a soft-start cycle, G2 is held low until
G1 first transitions high.
G1 (Pin 8): Gate Drive for the Topside N-Channel MOSFET,
Q1. This output swings from PV
CC
to GND. It is always low
if G2 is high or if the output is disabled.
PV
CC
(Pin 1): Power Supply for G1, G2 and Logic. PV
CC
must connect to a potential of at least V
IN
+ V
GS(ON)Q1
. If
V
IN
= 5V, generate PV
CC
using a simple charge pump
connected to the switching node between Q1 and Q2 (see
Figure 1) or connect PV
CC
to a 12V supply. Bypass PV
CC
properly or erratic operation will result. A low ESR 10µF
capacitor or larger bypass capacitor along with a 0.1µF
surface mount ceramic capacitor in parallel is recom-
mended from PV
CC
directly to GND to minimize switching
ripple. Switching ripple should be ≤100mV at the PV
CC
pin.
GND (Pin 2): Power and Logic Ground. GND is connected
to the internal gate drive circuitry and the feedback cir-
cuitry. To obtain good output voltage regulation, use
proper ground techniques between the LTC1530 GND and
bottom-side FET source and the negative terminal of the
output capacitor. See the Applications Information section
for more details on PCB layout techniques.
V
SENSE
/V
OUT
(Pin 3): Feedback Voltage Pin. For the adjust-
able LTC1530, use an external resistor divider to set the
required output voltage. Connect the tap point of the
resistor divider network to V
SENSE
and the top of the
divider network to the output voltage. For fixed output
voltage versions of the LTC1530, the resistor divider is
internal and the top of the resistor divider network is
brought out to V
OUT
. In general, the resistor divider
network for each fixed output voltage version sinks ap-
proximately 30µA. Connect V
OUT
to the output voltage
either at the output capacitors or at the actual point of load.
V
SENSE
/V
OUT
is sensitive to switching noise injected into
the pin. Isolate high current switching traces from this pin
and its PCB trace.
COMP (Pin 4): External Compensation. The COMP pin is
connected to the error amplifier output and the input of the
PWM comparator. An RC + C network is typically used at
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