13
Applications Information: Designing with the
MGA-72543 RFIC Ampli er/Bypass Switch
Description
The MGA-72543 is a single-stage, GaAs RFIC ampli er
with an
integrated bypass switch. A functional diagram of the
MGA-72543 is shown in Figure 1.
The MGA-72543 is designed for receivers and transmitters
operating from 100 MHz to 6 GHz with an emphasis on
1.9 GHz CDMA applications. The MGA-72543 combines
low noise performance with high linearity to make it
especially advantageous for use in receiver front-ends.
current range of 10 – 30 mA, the magnitude of É°opt at
1900 MHz is typically less than 0.25 and additional imped-
ance matching would only net about 0.1 dB improvement
in noise  gure.
Without external matching, the input return loss for the
MGA-72543 is approximately 5 dB at 1900 MHz. If desired,
a small amount of NF can be traded o for a signi cant
improvement in input match. For example, the addition
of a series inductance of 2.7 to 3.9 nH at the input of the
MGA-72543 will improve the input return loss to greater
than 10 dB with a sacri ce in NF of only 0.1 dB.
The output of the MGA-72543 is internally matched to
provide an output SWR of approximately 2:1 at 1900
MHz. Input and output matches both improve at higher
frequencies.
Driver Ampli er Applications
The  exibility of the adjustable current feature makes the
MGA-72543 suitable for use in transmitter driver stages.
Biasing the ampli er at 40 – 50 mA enables it to deliver
an output power at 1-dB gain compression of up to +16
dBm. Power e ciency in the unsaturated driver mode is
on the order of 30%. If operated as a saturated ampli er,
both output power and e ciency will increase.
Since the MGA-72543 is internally matched for low noise
gure, it may be desirable to add external impedance
matching at the input to improve the power match for
driver applications. Since the reactive part of the input
of the device impedance is capacitive, a series inductor
at the input is often all that is needed to provide a suit-
able match for many applications. For 1900 MHz circuits,
a series inductance of 3.9 nH will match the input to a
return loss of approximately 13 dB.
As in the case of low noise bias levels, the output of the
MGA-72543 is already well matched to 50 É∂ and no ad-
ditional matching is needed for most applications.
When used for driver stage applications, the bypass
switch feature of the MGA-72543 can be used to shut
down the ampli er to conserve supply current during
non-transmit periods. Supply current in the bypass state
is nominally 2 µA.
Biasing
Biasing the MGA-72543 is similar to biasing a discrete
GaAs FET. Passive biasing of the MGA-72543 may be ac-
complished by either of two conventional methods, either
by biasing the gate or by using a source resistor.
RF
OUTPUT
AMPLIFIER
BYPASS MODE
RF
INPUT
Figure 1. MGA-72543 Functional Diagram.
The purpose of the switch feature is to prevent distortion
of high signal levels in receiver applications by bypass-
ing the ampli er altogether. The bypass switch can be
thought of as a 1-bit digital AGC circuit that not only pre-
vents distortion by bypassing the MGA-72543 ampli er,
but also reduces front-end system gain by approximately
16 dB to avoid overdriving subsequent stages in the re-
ceiver such as the mixer.
An additional feature of the MGA-72543 is the ability to
externally set device current to balance output power
capability and high linearity with low DC power consump-
tion. The adjustable current feature of the MGA-72543
allows it to deliver output power levels in excess of +15
dBm (P1dB), thus extending its use to other system ap-
plications such as transmitter driver stages.
The MGA-72543 is designed to operate from a +3-volt
power supply and is contained in a miniature 4-lead,
SOT-343 (SC-70) package to minimize printed circuit
board space.
LNA Applications
For low noise ampli er applications, the MGA-72543 is
typically biased in the 10 – 20 mA range. Minimum NF
occurs at 20 mA as noted in the performance curve of
NFmin vs. Id. Biasing at currents signi cantly less than
10 mA is not recommended since the characteristics of
the device began to change very rapidly at lower currents.
The MGA-72543 is matched internally for low NF. Over a
14
Figure 5. Device Current vs. R
bias
.
The approximate value of the external resistor, Rbias, may
also be calculated from:
Rbias =
964
(1 – 0.112
Id)
Id
where Rbias is in ohms and Id is the desired device current
in mA.
The source resistor technique is the preferred and most
common method of biasing the MGA -72543.
• Gate Bias
Using this method, Pins 1 and 4 of the ampli er are DC
grounded and a negative bias voltage is applied to Pin 3
as shown in Figure 2. This method has the advantage of
not only DC, but also RF grounding both of the ground
pins of the MGA-72543. Direct RF grounding of the
devices ground pins results in slightly improved perfor-
mance while decreasing potential instabilities, especially
at higher frequencies. The disadvantage is that a negative
supply voltage is required.
• Source Resistor Bias
The source resistor method is the simplest way of biasing
the MGA -72543 using a single, positive supply voltage.
This method, shown in Figure 4, places the RF Input (Pin
3) at DC ground and requires both of the device grounds
(Pins 1 and 4) to be RF bypassed. Device current, Id, is
determined by the value of the source resistance, Rbias,
between either Pin 1 or Pin 4 of the MGA-72543 and DC
ground. Note: Pins 1 and 4 are connected internally in the
RFIC. Maximum device current (approximately 65 mA)
occurs for Rbias = 0.
OUTPUT
& V
d
INPUT
32
41
V
ref
OUTPUT
& V
d
INPUT
32
4
1
R
bias
Figure 2. Gate Bias Method.
DC access to the input terminal for applying the gate bias
voltage can be made through either a RFC or high imped-
ance transmission line as indicated in Figure 2.
The device current, Id, is determined by the voltage at
Vref (Pin 3) with respect to ground. A plot of typical Id vs.
Vref is shown in Figure 3. Maximum device current (ap-
proximately 65 mA) occurs at Vref = 0.
Figure 3. Device Current vs. Vref.
The device current may also be estimated from the fol-
lowing equation:
Vref = 0.11 I
d
– 0.96
where Id is in mA and Vref is in volts.
The gate bias method would not normally be used unless
a negative supply voltage was readily available. For refer-
ence, this is the method used in the characterization test
circuits shown in Figures 1 and 2 of the MGA-72543 data
sheet.
Figure 4. Source Resistor Bias.
A simple method recommended for DC grounding the
input terminal is to merely add a resistor from Pin 3 to
ground, as shown in Figure 4. The value of the shunt R can
be comparatively high since the only voltage drop across
it is due to minute leakage currents that in the µA range.
A value of 1 KΩ would adequately DC ground the input
while loading the RF signal by only 0.2 dB loss.
A plot of typical Id vs. Rbias is shown in Figure 5.
0
10
50
40
30
20
-0.80 -0.70 -0.60 -0.50 -0.40 -0.20-0.30
I
d
(mA)
V
ref
(V)
0
10
60
50
40
30
20
040
20 60 80 100 140120
I
d
(mA)
R
bias
()
15
• Adaptive Biasing
For applications in which input power levels vary over a
wide range, it may be useful to dynamically adapt the bias
of the MGA-72543 to match the signal level. This involves
sensing the signal level at some point in the system and
automatically adjusting the bias current of the ampli  er
accordingly. The advantage of adaptive biasing is con-
servation of supply current (longer battery life) by using
only the amount of current necessary to handle the input
signal without distortion.
Adaptive biasing of the MGA-72543 can be accomplished
by either analog or digital means. For the analog control
case, an active current source (discrete device or IC) is
used in lieu of the source bias resistor. For simple digital
control, electronic switches can be used to control the
value of the source resistor in discrete increments. Both
methods of adaptive biasing are depicted in Figure 6.
A DC blocking capacitor at the output of the RFIC isolates
the supply voltage from succeeding circuits. If the source
resistor method of biasing is used, the RF input terminal of
the MGA-72543 is at DC ground potential and a blocking
capacitor is not required unless the input is connected di-
rectly to a preceding stage that has a DC voltage present.
Figure 6. Adaptive Bias Control.
Figure 7. DC Schematic for Gate Bias.
Figure 8. DC Schematic of Source Resistor Biasing.
• Biasing for Higher Linearity or Output Power
While the MGA-72543 is designed primarily for use up
to 50 mA in +3 volt applications, the output power can
be increased by using higher currents and/or higher
supply voltages. If higher bias levels are used, appropriate
caution should be observed for both the thermal limits
and the Absolute Maximum Ratings.
As a guideline for operation at higher bias levels, the
Maximum Operating conditions shown in the data sheet
table of Absolute Maximum Ratings should be followed.
This set of conditions is the maximum combination of
bias voltage, bias current, and device temperature that is
recommended for reliable operation. Note: In contrast to
Absolute Maximum ratings, in which exceeding any one
parameter may result in damage to the device, all of the
Maximum Operating conditions may reliably be applied
to the MGA-72543 simultaneously.
Analog
Control
32
41
Digital
Control
(b) Digital(a) Analog
32
41
RF
Output
RFC
V
d
= +2.5 V
Vref = -0.5 V
RF
Input
72
3
2
4
1
RF
Output
RFC
V
d
= +3 V
R
bias
RF
Input
72
3
2
4
1
• Applying the Device Voltage
Common to all methods of biasing, voltage Vd is applied
to the MGA-72543 through the RF Output connection (Pin
2). A RF choke is used to isolate the RF signal from the DC
supply. The bias line is capacitively bypassed to keep RF
from the DC supply lines and prevent resonant dips or
peaks in the response of the ampli er. Where practical, it
may be cost e ective to use a length of high impedance
transmission line (preferably /4) in place of the RFC.
When using the gate bias method, the overall device
voltage is equal to the sum of Vref at Pin 3 and voltage Vd
at Pin 2. As an example, to bias the device at the typical
operating voltage of 3 volts, Vd would be set to 2.5 volts
for a Vref of -0.5 volts. Figure 7 shows a DC schematic of
a gate bias circuit.
Just as for the gate bias method, the overall device
voltage for source resistor biasing is equal to Vref + Vd.
Since Vref is zero when using a source resistor, Vd is the
same as the device operating voltage, typically 3 volts. A
source resistor bias circuit is shown in Figure 8.

MGA-72543-TR1G

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
RF Amplifier 2.7-4.2 SV 14 dB
Lifecycle:
New from this manufacturer.
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