22
LTC1628/LTC1628-PG
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FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri-
mary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the V
IN
/V
OUT
ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
The secondary output voltage V
SEC
is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
V
SEC
(N + 1) V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≈+
08 1
6
5
If V
SEC
drops below this level, the FCB voltage forces
temporary continuous switching operation until V
SEC
is
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin Condition
0V to 0.75V Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
0.85V < V
FCB
< 4.3V Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors Regulating a Secondary Winding
>4.8V Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
The FLTCPL pin determines whether only the first or both
controllers are temporarily forced into continuous mode
when the FCB pin falls below 0.8V. Tying the FLTCPL pin
to ground will send only the first controller into continuous
operation while tying the FLTCPL pin to INTV
CC
will send
both controllers into continuous operation.
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC1628 by loading the I
TH
pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
I
TH
R
C
R
T1
INTV
CC
C
C
1628 F08
LTC1628
R
T2
Figure 8. Active Voltage Positioning Applied to the LTC1628
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loss from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
SENSE
,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of L,
R
SENSE
and ESR to obtain I
2
R losses. For example, if each
R
DS(ON)
= 30m, R
L
= 50m, R
SENSE
= 10m and R
ESR
= 40m (sum of both input and output capacitance
losses), then the total resistance is 130m. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V
OUT
for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 20m to 50m of ESR. The LTC1628 2-phase
architecture typically halves this input capacitance re-
quirement over competing solutions. Other losses includ-
ing Schottky conduction losses during dead-time and
inductor core losses generally account for less than 2%
total additional loss.
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear.com.)
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1628 circuits: 1) LTC1628 V
IN
current (in-
cluding loading on the 3.3V internal regulator), 2) INTV
CC
regulator current, 3) I
2
R losses, 4) Topside MOSFET
transition losses.
1. The V
IN
current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V
IN
current typically results in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
CC
to
ground. The resulting dQ/dt is a current out of INTV
CC
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
=f(Q
T
+Q
B
), where Q
T
and Q
B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch input
from an output-derived source will scale the V
IN
current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
CC
current results in approxi-
mately 2.5mA of V
IN
current. This reduces the mid-current
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Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.
The availability of the I
TH
pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response
. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1µs to 10µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
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LTC1628IG-PG#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 2-phase Step-dn + Pgood
Lifecycle:
New from this manufacturer.
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