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LTC1628/LTC1628-PG
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APPLICATIO S I FOR ATIO
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opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC1628 and occupy minimum PC trace area.
8. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from V
IN
to prevent the short-circuit
latchoff from occurring.
Reduce V
IN
from its nominal level to verify operation of the
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
IN
while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages, look for inductive coupling between C
IN
, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
