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8737AGI-11LFT

P1-P3P4-P6P7-P9P10-P12P13-P15
Low Skew ÷1/÷2
Differential-to- 3.3V LVPECL Clock Generator
8737I-11
DATA SHEET
8737I-11 REVISION C 7/16/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 8737I-11 is a low skew, high performance
Differential-to-3.3V LVPECL ClockGenerator/Divider.
The 8737I-11 has two selectable clock inputs. The CLK,
nCLK pair can acceptmost standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels.The clock enable is internally
synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics
make the 8737I-11 ideal for clock distribution applications
demanding well defi ned performance and repeatability.
FEATURES
• Two divide by 1 differential 3.3V LVPECL outputs;
Two divide by 2 differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Output skew: 75ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Bank skew: Bank A - 30ps (maximum)
Bank B - 45ps (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
8737I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
8737I-11 DATA SHEET
2 REVISION C 7/16/15
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1V
EE
Power Negative supply pin.
2 CLK_EN Power Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
3 CLK_SEL Input Pulldown
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
4 CLK Input Pulldown Non-inverting differential clock input.
5 nCLK Input Pullup Inverting differential clock input.
6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
7 nPCLK Input Pullup Inverting differential LVPECL clock input.
8 nc Unused No connect.
9 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset. When LOW, the Master Reset is disabled.
LVCMOS / LVTTL interface levels.
10, 13, 18 V
CC
Power Positive supply pins.
11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels.
14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels.
16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels.
19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
REVISION C 7/16/15
8737I-11 DATA SHEET
3 LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs Outputs
MR CLK_EN CLK_SEL Selected Source QA0, QA1 nQA0, nQA1 QB0, QB1 nQB0, nQB1
1 X X X LOW HIGH LOW HIGH
0 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH
0 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH
0 1 0 CLK, nCLK Enabled Enabled Enabled Enabled
0 1 1 PCLK, nPCLK Enabled Enabled Enabled Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Inputs Outputs
Input to Output Mode Polarity
CLK or PCLK nCLK or nPCLK QAx nQAx QBx nQBx
0 0 LOW HIGH LOW HIGH Differential to Differential Non Inverting
1 1 HIGH LOW HIGH LOW Differential to Differential Non Inverting
0 Biased; NOTE 1 LOW HIGH LOW HIGH Single Ended to Differential Non Inverting
1 Biased; NOTE 1 HIGH LOW HIGH LOW Single Ended to Differential Non Inverting
Biased; NOTE 1 0 HIGH LOW HIGH LOW Single Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH LOW HIGH Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
FIGURE 1 - CLK_EN TIMING DIAGRAM
P1-P3P4-P6P7-P9P10-P12P13-P15

8737AGI-11LFT

Mfr. #:
Buy 8737AGI-11LFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1:4 LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
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