MP20073DH-LF-Z

MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
MP20073 Rev. 1.0 www.MonolithicPower.com 4
10/16/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin # Name Description
1 DDQ
Power input for VTT regulator. Connect to GND through 10uF ceramic capacitor.
It is normally connected to the VDDQ of DDR memory rail.
2 VTT Power output for the VTT LDO.
3
GND,
Exposed Pad
The exposed pad and GND pin must be connected to the same ground plane.
4 VTTSEN Kelvin sensed feedback signal.
5 VDRV Chip bias Voltage.
6 REF LDO signal input for generating VDDQ/2 reference.
7 EN VTT regulator enable input. High to enable the chip.
8 VTTREF
Buffered output for the system. The receiving end of the DDR memory cells needs
this signal for their input comparator.
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
MP20073 Rev. 1.0 www.MonolithicPower.com 5
10/16/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS
C
1
=C
2
= C
3
=10µF, C
4
=C
6
=0.1µF, C
7
=4.7µF, V
DRV
=3.3V, T
A
=25
o
C, unless otherwise noted.
DDR2 Regulation DDR2 Source Regulation
Input Supply Current
vs. Temp
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Shut Down Input Current
vs. Temp
V
DDQ
=V
REF
=1.8V, V
TT
= 0V
DDR3 Source Regulation
Power Ramp Up
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Power Ramp Down
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Source Over Current Protection
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
V
TT
(V)
V
TT
(V)
I
TT
(A) I
TT
(A)
V
TT
(mV)
I
TT
(A)
V
TT
(mV)
I
TT
(A)
DDR3 Regulation
0.71
-3 -2.4 -1.2 1.20 2.4 3
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3
0.0
0.4
0.8
1.2
1.6
2.0
-40 -10 20 50 80 110 140
TEMPERATURE (
O
C)
INPUT CURRENT ( mA )
TEMPERATURE (
O
C)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
-40 -10 20 50 80 110 140
V
REF
2V/div.
V
TTREF
1V/div.
V
TT
0.5V/div.
I
TT
2A/div.
V
REF
2V/div.
V
DDQ
2V/div.
V
TT
0.5V/div.
I
TT
1A/div.
V
REF
2V/div.
V
DDQ
2V/div.
V
TT
0.5V/div.
I
TT
1A/div.
4ms/div.
10ms/div.
-3 -2.4 -1.2 1.20 2.4 3
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
MP20073 Rev. 1.0 www.MonolithicPower.com 6
10/16/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
C
1
=C
2
= C
3
=10µF, C
4
=C
6
=0.1µF, C
7
=4.7µF, V
DRV
=3.3V, T
A
=25
o
C, unless otherwise noted.
V
REF
2V/div.
V
TTREF
1V/div.
V
TT
0.5V/div.
V
TT
0.5V/div.
I
TT
2A/div.
I
TT
2A/div.
V
TT
20mV/div.
I
TT
1A/div.
V
TT
20mV/div.
I
TT
1A/div.
V
TT
0.5V/div.
I
TT
2A/div.
V
REF
2V/div.
V
TTEN
2V/div.
V
TT
1V/div.
I
TT
1A/div.
V
REF
2V/div.
V
TTEN
2V/div.
V
TT
1V/div.
I
TT
1A/div.
Enable On
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Enable Off
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Short Circuit
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Short Circuit Recovery
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Source Load Transient
V
DDQ
=V
REF
=1.8V, V
TT
= 0.9V
Sink Load Transient
V
DDQ
=V
REF
=1.5V, V
TT
= 0.75V
V
SINK
= 1.5V
µ
µ
µ

MP20073DH-LF-Z

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Power Management Specialized - PMIC 2A 1.3-6V DDR Memory Termination Reg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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