MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
MP20073 Rev. 1.0 www.MonolithicPower.com 4
10/16/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
PIN FUNCTIONS
Pin # Name Description
1 DDQ
Power input for VTT regulator. Connect to GND through 10uF ceramic capacitor.
It is normally connected to the VDDQ of DDR memory rail.
2 VTT Power output for the VTT LDO.
3
GND,
Exposed Pad
The exposed pad and GND pin must be connected to the same ground plane.
4 VTTSEN Kelvin sensed feedback signal.
5 VDRV Chip bias Voltage.
6 REF LDO signal input for generating VDDQ/2 reference.
7 EN VTT regulator enable input. High to enable the chip.
8 VTTREF
Buffered output for the system. The receiving end of the DDR memory cells needs
this signal for their input comparator.