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MC10H680FNR2

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1 Publication Order Number:
MC10H680/D
MC10H680, MC100H680
4−Bit Differential ECL Bus
to TTL Bus Transceiver
Description
The MC10H/100H680 is a dual supply 4−bit differential ECL bus to
TTL bus transceiver. It is designed to allow the system designer to no
longer be limited in bus speed associated with standard TTL busses.
Using a differential ECL Bus will increase the frequency of operation
and increase noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The
ECL outputs have the ability to drive 25 W, allowing both ends of the
bus line to be terminated in the characteristic impedance of 50 W. The
TTL outputs are specified to source 15 mA and sink 48 mA, allowing
the ability to drive highly capacitive loads.
The ECL output levels are V
OH
approximately equal to −1.0 V and
V
OL
cutoff equal to −2.0 V (VTT). When the ECL ports are disabled
both EIOx and EIOxB go to the V
OL
cutoff level. The ECL input
receivers have special circuitry which detects this disabled condition,
prevents oscillation, and forces the TTL output to the low state. The
noise margin in this disabled state is greater than 600 mV. Multiple
ECL V
CCO
pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have
PNP input devices to significantly reduce loading. Multiple TTL
power and ground pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is
compatible with MECL 10H™ ECL logic levels. The control pins of
the 100H version are compatible with 100K levels.
Features
• Differential ECL Bus (25 W) I/O Ports
• High Drive TTL Bus I/O Ports
• Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
• Dual Supply
• Direction and Chip Enable Control Pins
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
PLCC−28
FN SUFFIX
CASE 776
MCxxxH680G
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
MC10H680, MC100H680
http://onsemi.com
2
Figure 1. Pinout: PLCC−28 (Top View)
TIO2
GT3
VT2
GT4
TIO3
TCEB
ECEB
EIO0
EIO0B
EI01
EIO1B
V
CCO1
V
EE
V
CCO2
1
567891011
25 24 23 22 21 20 19
26
27
28
2
3
412
13
14
15
16
17
18
T101
GT2
VT1
GT1
TIO0
TDIR
EDIR
EIO3B
V
CCO4
EIO3
V
CCE
EIO2B
V
CCO3
EIO2
Table 1. PIN DESCRIPTIONS
Pin Symbol Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GT1
TIO0
TDIR
EDIR
EIO0
VCCO1
EIO0B
V
EE
EIO1
VCCO2
EIO1B
EIO2
VCCO3
EIO2B
V
CCE
EIO3
VCCO4
EIO3B
ECEB
TCEB
TIO3
GT4
VT2
GT3
TIO2
TIO1
GT2
VT1
TTL Ground 1
TTL I/O Bit 0
TTL Direction Control
ECL Direction Control
ECL I/O Bit 0
ECL V
CC
1 (0 V) − Outputs
ECL I/O Bit 0 Bar
ECL Supply (−5.2/−4.5 V)
ECL I/O Bit 1
ECL V
CC
2 (0 V) − Outputs
ECL I/O Bit 1 Bar
ECL I/O Bit 2
ECL V
CC
3 (0 V) − Outputs
ECL I/O Bit 2 Bar
ECL V
CC
(0 V)
ECL I/O Bit 3
ECL V
CC
4 (0 V) − Outputs
ECL I/O Bit 3 Bar
ECL Chip Enable Bar Control
TTL Chip Enable Bar Control
TTL I/O Bit 3
TTL Ground 4
TTL Supply 2 (5.0 V)
TTL Ground 3
TTL I/O Bit 2
TTL I/O Bit 1
TTL Ground 2
TTL Supply 1 (5.0 V)
Table 2. TRUTH TABLE
ECEB TCEB EDIR TDIR EIN EINB EOUT EOUTB TIN TOUT COMMENTS
H X X X X X LC LC X Z ECL and TTL Outputs Disabled
X H X X X X LC LC X Z ECL and TTL Outputs Disabled
L L H X H LC NA H ECL to TTL Direction
L L H X LC H NA L ECL to TTL Direction
L L H X LC LC NA L ECL to TTL Direction (L−L Condition)
L L X H H LC NA H ECL to TTL Direction
L L X H LC H NA L ECL to TTL Direction
L L X H LC LC NA L ECL to TTL Direction (L−L Condition)
L L L L NA NA H LC H TTL to ECL Direction
L L L L NA NA LC H L TTL to ECL Direction
TDIR − Direction Control TTL Levels
EDIR − Direction Control ECL Levels
TCEB − Chip Enable Bar Control TTL Levels
H − HIGH
L − LOW
LC − ECL Low Cutoff (VTT = −2.0 V)
X − Don’t Care
Z − High Impedance
ECEB − Chip Enable Bar Control ECL Levels
TIN − TTL Input
TOUT − TTL Output
EIN − ECL Input
EINB − ECL Input Bar
EOUT − ECL Output
EOUTB − ECL Output Bar
MC10H680, MC100H680
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Parameter Symbols Rating Unit
Power Supply Voltage V
EE
(ECL) −8.0 to 0 Vdc
Power Supply Voltage V
CCT
(TTL) −0.5 to +7.0 Vdc
Input Voltage V
I
(ECL)
V
I
(TTL)
0.0 to V
EE
−0.5 to +7.0
Vdc
Disabled 3−State Output V
out
(TTL) 0.0 to V
CCT
Vdc
Output Source Current Continuous I
out
(ECL) 100 mAdc
Output Source Current Surge I
out
(ECL) 200 mAdc
Storage Temperature T
stg
−65 to 150 °C
Operating Temperature T
amb
0.0 to +75 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. DC CHARACTERISTICS, ECL V
CCT
= + 5.0 V ±10%, V
EE
= − 5.2 ± 5% (10H Version);
V
EE
= − 4.2 V to − 5.5 V (100H Version)
Symbol
T
A
= 0°C T
A
= 25°C T
A
= 75°C
Parameter Condition Min Max Min Max Min Max Unit
I
EE
Supply Current/ECL −110 −110 −110 mA
I
INH
Input HIGH Current 255 175 175
mA
I
INL
Input LOW Current 0.5 0.5 0.3
mA
V
OH
V
OL
Output HIGH Voltage
Output LOW Voltage
25 W to − 2.1 V
−1100
−2.1
−840
−2.03
−1100
−2.1
−810
−2.03
−1100
−2.1
−735
−2.03
mV
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. 10H DC CHARACTERISTICS (CONTROL INPUTS ONLY), ECL V
CCT
= + 5.0 ±10%, V
EE
= − 5.2 ± 5%
Symbol
T
A
= 05C T
A
= 255C T
A
= 755C
Parameter Min Max Min Max Min Max Unit
V
IH
V
IL
Input HIGH Voltage
Input LOW Voltage
−1170
−1950
−840
−1480
−1130
−1950
−810
−1480
−1070
−1950
−735
−1450
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
P1-P3P4-P6P7-P9P10-P10

MC10H680FNR2

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Manufacturer:
ON Semiconductor
Description:
IC TRNSLTR BIDIRECTIONAL 28PLCC
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