ADCMP603 Data Sheet
Rev. A | Page 10 of 16
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP603 comparator is a very high speed device. Despite
the low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any phase
relationship is likely to cause oscillations or undesired hysteresis. Of
critical importance is the use of low impedance supply planes,
particularly the output supply plane (V
CCO
) and the ground plane
(GND). Individual supply planes are recommended as part of a
multilayer board. Providing the lowest inductance return path for
switching currents ensures the best possible performance in the
target application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
CCI
and V
CCO
supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V
CCO
pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
If the input and output supplies have been connected separately
such that V
CCI
≠ V
CCO
, care should be taken to bypass each of
these supplies separately to the GND plane. A bypass between
them is futile and defeats the purpose of having separate pins. It
is recommended that the GND plane separate the V
CCI
and V
CCO
planes when the circuit board layout is designed to minimize
coupling between the two supplies and to take advantage of the
additional bypass capacitance from each respective supply to
the ground plane. This enhances the performance when split
input/output supplies are used. If the input and output supplies are
connected together for single-supply operation such that V
CCI
=
V
CCO
, coupling between the two supplies is unavoidable; however,
careful board placement can help keep output return currents
away from the inputs.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified minimums.
The low skew complementary outputs of the ADCMP603 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or the equivalent. For large fan outputs,
buses, or transmission lines, use an appropriate buffer to
maintain the excellent speed and stability of the comparator.
With the rated 5 pF load capacitance applied, more than half of
the total device propagation delay is output stage slew time,
even at 2.5 V V
CC
. Because of this, the total prop delay decreases
as V
CCO
decreases, and instability in the power supply may
appear as excess delay dispersion.
This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the V
CC
supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
When duty cycle accuracy is critical, the logic being driven
should switch at 50% of V
CC
and load capacitance should be
minimized. When in doubt, it is best to power V
CCO
or the
entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and V
CC
variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 14). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
OUTPUT
Q2
Q1
IN
IN
OUTPUT STAGE
V
LOGIC
GAIN STAGE
A2
A1
A
V
5915-012
Figure 14. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating for fixed hysteresis or be tied to V
CC
to
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of V
CC
.
