Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2
2004 Feb 27
FEATURES
• 16-bit transparent latch
• Multiple V
CC
and GND pins minimize switching noise
• Power-up 3-State
• Live insertion/extraction permitted
• Power-up reset
• 3-State output buffers
• Output capability: +64 mA/–32 mA
• I
CCL
–19 mA maximum
• Latch-up protection exceeds 500 mA per JEDEC Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE
) control gates.
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is HIGH. The latch remains
transparent to the data inputs while nE is HIGH, and stores the data
that is present one set-up time before the HIGH-to-LOW enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE
) controls eight 3-State buffers
independent of the latch operation.
When nOE
is LOW, the latched or transparent data appears at the
outputs. When nOE
is HIGH, the outputs are in the high-impedance
“OFF” state, which means they will neither drive nor load the bus.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q3
V
CC
2Q4
V
CC
2Q2
2Q5
GND
2Q7
2OE
2Q6
1E
1D0
1D1
GND
1D2
1D3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D3
V
CC
2D4
V
CC
2D2
2D5
GND
2D7
2E
2D6
SA00379
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25 °C; GND = 0 V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
Dn to Qn
C
L
= 50 pF; V
CC
= 5 V
2.5
2.0
ns
C
IN
Input capacitance V
I
= 0 V or V
CC
4 pF
C
OUT
Output capacitance V
O
= 0 V or V
CC
; 3-State 7 pF
I
CCZ
pp
Outputs disabled; V
CC
= 5.5 V 500 µA
I
CCL
u
u
y
u
Outputs low; V
CC
= 5.5 V 8 mA
ORDERING INFORMATION
T
amb
= –40
°
C to +85
°
C
Type number
Package
Name Description Version
74ABT16373BDL SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
74ABT16373BDGG TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
