Philips Semiconductors Product data
74ABT16373B16-bit transparent latch (3-State)
2004 Feb 27
7
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
V
M
nDx
V
M
V
M
V
M
V
M
nE
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
SA00049
V
M
Waveform 3. Data Set-up and Hold Times
nOE
V
M
t
PZH
t
PHZ
0V
nQx
V
M
V
M
SA00050
V
OH
V
OH
– 0.3V
Waveform 4. 3-State Output Enable Time to HIGH Level and
Output Disable Time from HIGH Level
nOE
t
PZL
t
PLZ
nQx
V
M
V
M
V
M
SA00051
V
OL
+ 0.3V
V
OL
Waveform 5. 3-State Output Enable Time to LOW Level and
Output Disable Time from LOW Level
TEST CIRCUIT AND WAVEFORM
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
R
L
V
CC
R
L
7.0 V
Test Circuit for 3-State Outputs
V
M
V
M
t
W
AMP (V)
NEGATIVE
PULSE
10% 10%
90%
90%
0 V
V
M
V
M
t
W
AMP (V)
POSITIVE
PULSE
90% 90%
10%
10%
0 V
t
THL
(t
F
)
t
TLH
(t
R
)t
THL
(t
F
)
t
TLH
(t
R
)
V
M
= 1.5 V
Input Pulse Definition
DEFINITIONS
R
L
= Load resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude Rep. Rate t
W
t
R
t
F
74ABT 3.0 V 1 MHz 500 ns 2.5 ns 2.5 ns
SWITCH POSITION
TEST SWITCH
t
PLZ
closed
t
PZL
closed
All other open
SA00654
C
L
