BSS84_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 16 December 2008 3 of 11
NXP Semiconductors
BSS84
P-channel enhancement mode vertical DMOS transistor
5. Limiting values
[1] Device mounted on a Printed-Circuit Board (PCB).
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage 25 °C ≤ T
j
≤ 150 °C-−50 V
V
GS
gate-source voltage - ±20 V
I
D
drain current T
sp
=25°C; V
GS
= −10 V;
see
Figure 1
- −130 mA
T
sp
= 100 °C;
V
GS
= −10 V
- −75 mA
I
DM
peak drain current T
sp
=25°C; t
p
≤ 10 µs;
see
Figure 1
- −520 mA
P
tot
total power dissipation T
sp
=25°C; see Figure 2
[1]
- 250 mW
T
stg
storage temperature −65 +150 °C
T
j
junction temperature −65 +150 °C
T
sp
=25°C
(1) R
DSon
limitation
Fig 1. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
mld251
V
DS
(V)
−1 −10
2
−10
−10
2
−10
−10
3
I
D
(mA)
−1
1 ms
10 ms
100 ms
DC
(1)
t
p
=
10 µs
100 µs
