MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
4 Freescale Semiconductor
Electrical and Thermal Characteristics
4.3.1 Clock AC Specifications
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation for
29 angstrom parts. These graphs define the areas of DLL locking for various modes. The gray areas show
where the DLL will lock.
I/O Power Supplies
10
Mode Range Unit Notes
Typ— OV
DD
140–360 mW 7, 8
Typ— GV
DD
340–920 mW 7, 9
Notes:
1. The values include V
DD
, AV
DD
, and AV
DD
2, but do not include I/O supply power.
2. Maximum—FP power is measured at V
DD
= 2.1 V with dynamic power management enabled while running an entirely
cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at V
DD
= 2.1 V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at V
DD
= 2.1 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at V
DD
= AV
DD
= 2.1 V, OV
DD
= 3.3 V where a nominal FP value, a nominal INT value, and a
value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory
are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the
slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8. The typical maximum OV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of 66:133:399
(PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating ones and
zeros to PCI memory.
9. The typical maximum GV
DD
value resulted from the MPC8245 operating at the fastest frequency combination of
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating
ones and zeros on 64-bit boundaries to local memory.
10. Power consumption of PLL supply pins (AV
DD
and AV
DD
2) < 15 mW that the design guarantees but were not tested.
Table 5. Power Consumption (continued)
Mode
PCI Bus Clock/Memory
Bus Clock
CPU Clock Frequency
(MHz)
Unit Notes
66/133/399
