CY7C4261, CY7C4271
16K/32K x 9 Deep Sync FIFOs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06015 Rev. *D Revised August 22, 2008
Features
■ High speed, low power, first-in first-out (FIFO) memories
■ 16K × 9 (CY7C4261)
■ 32K × 9 (CY7C4271)
■ 0.5 micron CMOS for optimum speed and power
■ High speed 100 MHz operation (10 ns read/write cycle times)
■ Low power — I
CC
= 35 mA
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
■ TTL compatible
■ Output Enable (OE) pins
■ Independent read and write enable pins
■ Center power and ground pins for reduced noise
■ Supports free running 50% duty cycle clock inputs
■ Width Expansion Capability
■ Military temp SMD Offering – CY7C4271-15LMB
■ 32-pin PLCC/LCC and 32-pin TQFP
■ Pin compatible density upgrade to CY7C42X1 family
■ Pin compatible density upgrade to IDT72201/11/21/31/41/51
■ Pb-Free Packages Available
Functional Description
The CY7C4261/71 are high speed, low power FIFO memories
with clocked read and write interfaces. All are nine bits wide. The
CY7C4261/71 are pin compatible to the CY7C42X1
Synchronous FIFO family. The CY7C4261/71 can be cascaded
to increase FIFO width. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high speed data
acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1
, WEN2/LD).
When WEN1
is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1
,
WEN2/LD
is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a free running read clock (RCLK) and two read enable
pins (REN1
, REN2). In addition, the CY7C4261/71 has an output
enable pin (OE
). The read (RCLK) and write (WCLK) clocks may
be tied together for single-clock operation or the two clocks may
be run independently for asynchronous read/write applications.
Clock frequencies up to 100 MHz are achievable. Depth
expansion is possible using one enable input for system control,
while the other enable is controlled by expansion logic to direct
the flow of data.
Selection Guide
Parameter 7C4261/71-10 7C4261/71-15 7C4261/71-25 7C4261/71-35 Unit
Maximum Frequency 100 66.7 40 28.6 MHz
Maximum Access Time 8 10 15 20 ns
Minimum Cycle Time 10 15 25 35 ns
Minimum Data or Enable Setup3467ns
Minimum Data or Enable Hold 0.5 1 1 2 ns
Maximum Flag Delay 8 10 15 20 ns
Active Power Supply
Current (I
CC1
)
Commercial 35 35 35 35 mA
Industrial/
Military
40 40 40 40
Parameter CY7C4261 CY7C4271
Density 16K × 9 32K × 9
Package 32-pin PLCC, TQFP 32-pin LCC, PLCC, TQFP
[+] Feedback
