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CY7C4261-15JXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY7C4261, CY7C4261
Document #: 38-06015 Rev. *D Page 10 of 19
Figure 8. Reset Timing
[16]
Figure 9. First Data Word Latency after Reset with Read and Write
Switching Waveforms (continued)
t
RS
t
RSR
Q
0-
Q
8
RS
t
RSF
t
RSF
t
RSF
OE = 1
OE = 0
REN1
,
REN2
EF,PAE
FF,PAF
t
RSS
t
RSR
t
RSS
t
RSR
t
RSS
WEN2/LD
WEN1
[18]
[17]
D
0
(FIRST VALID WRITE)
t
SKEW1
WEN1
WCLK
Q
0
–Q
8
EF
REN1,
REN2
OE
t
OE
t
ENS
t
OLZ
t
DS
RCLK
t
REF
t
A
t
FRL
D
1
D
2
D
3
D
4
D
0
D
1
D
0
–D
8
t
A
WEN2
(if applicable)
[19]
[20]
Notes
16. The clocks (RCLK, WCLK) can be free running during reset.
17. After reset, the outputs are LOW if OE
= 0 and three-state if OE = 1.
18. Holding WEN2/LD
HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the
programmable flag offset registers.
19. When t
SKEW1
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW2
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or t
CLK
+
t
SKEW1
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF
goes HIGH, always.
[+] Feedback
CY7C4261, CY7C4261
Document #: 38-06015 Rev. *D Page 11 of 19
Figure 10. Empty Flag Timing
Figure 11. Full Flag Timing
Switching Waveforms (continued)
DATA WRITE 2
DATA WRITE 1
t
ENS
t
SKEW1
DATA IN OUTPUT REGISTER
WEN1
WCLK
Q
0
–Q
8
EF
REN1,
REN2
OE
t
DS
t
ENH
RCLK
t
REF
t
A
t
FRL
D
0
–D
8
DATA READ
t
SKEW1
t
FRL
t
REF
t
DS
t
ENS
t
ENH
t
ENS
WEN2
(if applicable)
t
ENH
t
ENS
t
ENH
t
REF
LOW
[19] [19]
Q
0
–Q
8
REN1,
REN2
WEN1
WEN2
(if applicable)
D
0
–D
8
NEXT DATA READ
DATA WRITE
NO WRITE
DATA IN OUTPUT REGISTER
FF
WCLK
OE
RCLK
t
A
DATA READ
t
SKEW1
t
DS
t
ENS
t
ENH
t
WFF
t
A
t
SKEW1
t
ENS
t
ENH
t
WFF
DATA WRITE
NO WRITE
t
WFF
LOW
[14]
[14]
[+] Feedback
CY7C4261, CY7C4261
Document #: 38-06015 Rev. *D Page 12 of 19
Figure 12. Programmable Almost Empty Flag Timing
Figure 13. Programmable Almost Full Flag Timing
Switching Waveforms (continued)
t
ENH
WCLK
PAE
RCLK
t
CLKH
t
ENS
t
CLKL
t
ENS
t
PAE
N + 1 WORDS
IN FIFO
t
ENH
t
ENS
t
ENH
t
ENS
t
PAE
REN1,
REN2
WEN1
WEN2
(if applicable)
t
ESKEW2
[21]
22
23
Note
t
ENH
WCLK
PAF
RCLK
t
CLKH
t
ENS
FULL − M WORDS
IN FIFO
t
CLKL
t
ENS
FULL − (M + 1) WORDS
IN FIFO
t
ENH
t
ENS
t
ENH
t
ENS
t
PAF
REN1,
REN2
WEN1
WEN2
(if applicable)
t
SKEW2
t
PAF
[26]
[27]
24
25
Notes
21. t
SKEW2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
and the rising RCLK is less than t
SKEW2
, then PAE may not change state until the next RCLK.
22. PAE offset= n.
23. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE
goes LOW
24. If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF
goes LOW.
25. PAF offset = m.
26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271.
27. t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of
RCLK and the rising edge of WCLK is less than t
SKEW2
, then PAF may not change state until the next WCLK.
[+] Feedback
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY7C4261-15JXC

Mfr. #:
Buy CY7C4261-15JXC
Manufacturer:
Cypress Semiconductor
Description:
IC DEEP SYNC FIFO 16KX9 32-PLCC
Lifecycle:
New from this manufacturer.
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