PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 14 of 27
NXP Semiconductors
PCA9542A
2-channel I
2
C-bus multiplexer and interrupt logic
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20 typical R
on
and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] C
b
= total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 10. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
t
PD
propagation delay from SDA to SDx,
or SCL to SCx
-0.3
[1]
-0.3
[1]
ns
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
HD;STA
hold time (repeated) START
condition
[2]
4.0 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
HIGH
HIGH period of the SCL clock 4.0 - 0.6 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4.0 - 0.6 - s
t
HD;DAT
data hold time 0
[3]
3.45 0
[3]
0.9 s
t
SU;DAT
data set-up time 250 - 100 - ns
t
r
rise time of both SDA and SCL
signals
- 1000 20 + 0.1C
b
[4]
300 ns
t
f
fall time of both SDA and SCL
signals
-30020+0.1C
b
[4]
300 ns
C
b
capacitive load for each bus line - 400 - 400 pF
t
SP
pulse width of spikes that must be
suppressed by the input filter
-50 - 50ns
t
VD;DAT
data valid time HIGH-to-LOW
[5]
-1 - 1s
LOW-to-HIGH
[5]
-0.6 - 0.6s
t
VD;ACK
data valid acknowledge time - 1 - 1 s
INT
t
v(INTnN-INTN)
valid time from INTn to INT signal
[5]
-4 - 4s
t
d(INTnN-INTN)
delay time from INTn to INT inactive
[5]
-2 - 2s
t
w(rej)L
LOW-level rejection time INTn inputs
[5]
1- 1 -s
t
w(rej)H
HIGH-level rejection time INTn inputs
[5]
0.5 - 0.5 - s
