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74FCT162511CTPAG8

P1-P3P4-P6P7-P9P10-P10
4
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
NOTES:
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB
= H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the
corresponding data regardless of parity errors (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
clock.
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag PERB is a combined flag for both bytes A0–A7 and A8–A15. If a parity
error occurs on either byte PERB will go low. PERB is an open drain output which must
be externally pulled up to achieve a logic HIGH.
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
triggered clock.
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
the parity on PB2.
5. The error flag PERB will remain in a high state during parity generation.
FUNCTION TABLE
(1, 4)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
and CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
Inputs Outputs
OEAB LEAB CLKAB Ax Bx
HXXXZ
LHXLL
LHXHH
LL↑ LL
LL↑ HH
LLLXB
(2)
LLHXB
(3)
A0 – A7
Number of inputs that are high ODD/EVEN PB1
1, 3, 5 or 7 L H
1, 3, 5 or 7 H L
0, 2, 4, 6 or 8 L L
0, 2, 4, 6 or 8 H H
A
0 – A7 and PA1
(5)
Number of inputs that are high ODD/EVEN PERB
1, 3, 5, 7 or 9 L L
1, 3, 5, 7 or 9 H H
(6)
0, 2, 4, 6 or 8 L H
(6)
0, 2, 4, 6 or 8 H L
FUNCTION TABLE
(PARITY CHECKING)
(1, 2, 3, 4)
FUNCTION TABLE
(PARITY GENERATION)
(1, 2, 3, 4, 5)
5
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
V
IH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
I
IH Input HIGH Current (Input pins)
(5)
VCC = Max. VI = VCC —— ±1µA
Input HIGH Current (I/O pins)
(5)
—— ±1
I
IL Input LOW Current (Input pins)
(5)
VI = GND — — ±1
Input LOW Current (I/O pins)
(5)
—— ±1
I
OZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA
IOZL (3-State Output pins)
(5)
VO = 0.5V — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND
(3)
–80 –140 –250 mA
VH Input Hysteresis — — 100 — mV
I
CCL Quiescent Power Supply Current VCC = Max. — 5 500 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = –55°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
IODL Output LOW (I/O pins) VCC = 5V, VIN = VIH or VIL, VO = 1.5V
(3)
60 115 200 mA
Current (Open Drain) — 250 — mA
IODH Output HIGH Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V
(3)
–60 –115 –200 mA
I
OFF Output Power Off Leakage Current VCC = 0, VO ≤ 5.5V — — ±1 µ A
(Open Drain)
(5)
VOH Output HIGH Voltage (I/O pins) VCC = Min. IOH = –16mA MIL 2.4 3.3 — V
VIN = VIH or VIL IOH = –24mA IND
V
OL Output LOW (I/O pins) VCC = Min. IOL = 16mA MIL — 0.3 0.55 V
Voltage VIN = VIH or VIL IOL = 24mA IND
(Open Drain) I
OL = 48mA MIL — 0.3 0.55 V
I
OL = 64mA IND
6
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
ΔICC Quiescent Power Supply Current VCC = Max. All other Input Pins — 0.5 1.5 mA
TTL Inputs HIGH VIN = 3.4V
(3)
Parity Input Pins (PAx, PBx) — 1 2.5
I
CCD Dynamic Power Supply VCC = Max. VIN = VCC — 75 120 µ A /
Current
(4)
Outputs Open VIN = GND MHz
OEAB = GND, OEBA = V
CC
One Input Togging
50% Duty Cycle
I
C Total Power Supply Current
(6)
VCC = Max. VIN = VCC — 0.8 1.7 mA
Outputs Open V
IN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
LEAB = GND VIN = 3.4V — 1.3 3.2
One Bit Toggling V
IN = GND
fi = 5MHz
50% Duty Cycle
V
CC = Max. VIN = VCC — 3.8 6.5
(5)
Outputs Open VIN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
LEAB = GND VIN = 3.4V — 9 21.8
(5)
Eighteen Bits Toggling VIN = GND
fi = 2.5MHz
50% Duty Cycle
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
P1-P3P4-P6P7-P9P10-P10

74FCT162511CTPAG8

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Buy 74FCT162511CTPAG8
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Description:
IC TXRX NON-INVERT 5.5V 56TSSOP
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